참고문헌
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피인용 문헌
- A 5.5-GHz CMOS power amplifier using parallel-combined transistors with cascode adaptive biasing for WLAN applications vol.15, pp.9, 2018, https://doi.org/10.1587/elex.15.20180336
- Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules vol.8, pp.2, 2019, https://doi.org/10.3390/electronics8020210