Journal of Satellite, Information and Communications (한국위성정보통신학회논문지)

Korea Society of Satellite Technology (한국위성정보통신학회)
권호 표지

Simulation-based ESD protection performance of modified DDD_NSCR device with counter pocket source structure for high voltage operating I/O application

고전압 동작용 I/O 응용을 위해 Counter Pocket Source 구조를 갖도록 변형된 DDD_NSCR 소자의 ESD 보호성능 시뮬레이션

  • 서용진 (세한대학교 소방행정학과/나노정보소재연구소) ;
  • 양준원 (세한대학교 항공교통물류학과)
  • Received : 2016.11.22
  • Accepted : 2016.12.06
  • Published : 2016.12.31
Download PDF
⟨ Previous Next ⟩

Abstract

A conventional double diffused drain n-type MOSFET (DDD_NMOS) device shows SCR behaviors with very low snapback holding voltage and latch-up problem during normal operation. However, a modified DDD_NMOS-based silicon controlled rectifier (DDD_NSCR_CPS) device with a counter pocket source (CPS) structure is proven to increase the snapback holding voltage and on-resistance compare to standard DDD_NSCR device, realizing an excellent electrostatic discharge protection performance and the stable latch-up immunity.

종래의 이중 확산된 드레인을 갖는 n형 MOSFET(DDD_NMOS) 소자는 매우 낮은 스냅백 홀딩 전압을 갖는 SCR 특성을 나타내므로 정상적인 동작 동안 래치업 문제를 초래한다. 그러나, 본 연구에서 제안하는 counter pocket source (CPS) 구조를 갖도록 변형된 DDD_NMOS 구조의 SCR 소자는 종래의DDD_NSCR_Std 표준소자에 비해 스냅백 홀딩 전압과 온-저항을 증가시켜 우수한 정전기 보호 성능과 높은 래치업 면역 특성을 얻을 수 있는 것으로 확인되었다.

Keywords

References

  1. Mergens M, Wilkening W, Mettler S, Wolf H, Stricker A, Fichtner W, "Analysis of lateral DMOS power devices under ESD stress conditions", IEEE Trans Electron Devices, 47(11), pp.2128-2137, 2000. https://doi.org/10.1109/16.877175
  2. Dabral S, Maloney T, "Basic ESD and I/O Design", John Wiley & Sons, 1998.
  3. Jeon B-C, Lee S-C, Oh J-K, Kim S-S, Han M-K, Jung Y-I, Kim K-H, "ESD characterization of grounded-gate NMOS with 0.35 lm/18 V technology employing transmission line pulser (TLP) test", In Proceedings of the EOS/ESD symposium, pp.362-372, 2002.
  4. Kim K-H, Jung, Y-I, Shim, J-S, So H-T, Lee J-H, Hwang L-Y, Park J-W, "Illumination of double snapback mechanism in high voltage operating grounded gate extended drain N-type metal-oxide-semiconductor field effects transistor electro-static discharge protection devices", Japanese journal of applied physics, 43(10), pp.6930-6936, 2004. https://doi.org/10.1143/JJAP.43.6930
  5. Chatterjee A, Polgreen T, "A low-voltage triggering SCR for on-chip ESD protection at output and input pads", IEEE Electron Device Lett., 12(1), pp.21-22, 1991. https://doi.org/10.1109/55.75685
  6. Lee J-H, Shih J-R, Tang C-S, Liu K-C, Wu Y-H, Shiue R-Y, T-C. Ong, Y'-K Peng, J-T Yue,"Novel ESD protection structure with embedded SCR LDMOS for smart power technology", In Proceedings of the IEEE 40th annual international reliability physics symposium, pp.156-161, 2002.
  7. Ker M-D, Chang H-H, Wu C-Y, "A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's", IEEE J Solid-State Circuits, 32(1), pp.38-51, 1997. https://doi.org/10.1109/4.553176
  8. Lai C-H, Liu M-H, Su S, Lu T-C, Pan S, "A novel gate-coupled SCR ESD protection structure with high latchup immunity for high-speed I/O pad", IEEE Electron Device Lett., 25(5), pp.328-330, 2004. https://doi.org/10.1109/LED.2004.826529
  9. Ker MD, "Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology", IEEE Trans Electron Dev., 45(4), pp.849-860, 1998. https://doi.org/10.1109/16.662790
  10. Mergens M, Russ C, Verhaege K, Armer J, Jozwiak P, Mohn R, "High holding current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation", In Proceedings of the EOS/ESD symposium, pp.14-21, 2002.
  11. Streibl M, Esmark K, Sieck A, Stadler W, Wendel M, Szatkowski J, Gobner H, "Harnessing the base-pushout effect for ESD protection in bipolar and BiCMOS technologies", In Proceedings of the EOS/ESD symposium, pp.73-82, 2002.
  12. Kim K-H, Seo Y-J, "Electronic discharge (ESD) protection of N-type silicon controlled rectifier with P-type MOSFET pass structure for high voltage operating I/O application", Microelectronics Reliability, 53(2), pp.205-207, 2013. https://doi.org/10.1016/j.microrel.2012.04.014