High Performance ESD/Surge Protection Capability of Bidirectional Flip Chip Transient Voltage Suppression Diodes

Abstract

We have developed new electrostatic discharge (ESD) protection devices with, bidirectional flip chip transient voltage suppression. The devices differ in their epitaxial (epi) layers, which were grown by reduced pressure chemical vapor deposition (RPCVD). Their ESD properties were characterized using current-voltage (I-V), capacitance-voltage (C-V) measurement, and ESD analysis, including IEC61000-4-2, surge, and transmission line pulse (TLP) methods. Two BD-FCTVS diodes consisting of either a thick (12 μm) or thin (6 μm), n-Si epi layer showed the same reverse voltage of 8 V, very small reverse current level, and symmetric I-V and C-V curves. The damage found near the corner of the metal pads indicates that the size and shape of the radius governs their failure modes. The BD-FCTVS device made with a thin n- epi layer showed better performance than that made with a thick one in terms of enhancement of the features of ESD robustness, reliability, and protection capability. Therefore, this works confirms that the optimization of device parameters in conjunction with the doping concentration and thickness of epi layers be used to achieve high performance ESD properties.

1. INTRODUCTION

Electrostatic discharge (ESD) is a well-known transient threat to sensitive integrated circuit (IC) components.[1-3] The phenomenon of ESD leads to permanent device damage associated with the breakdowns of junctions, metal interconnects and dielectrics, caused by high current transients and high voltage overstress. Nowadays, IC dimensions have been continuously scaled down to realize higher packing density, faster operation speed and lower power dissipation. Hence, ICs are more vulnerable than before to the damaging effects associated with ESD events [1,4]. However, the ICs still suffer from reliability problems owing to ESD. It was reported that approximately 35% of total IC failures are related to ESD, incurring tremendous annual costs to the IC industry [5,6].

It is therefore, important to improve the ESD protection devices with lower breakdown voltage, lower capacitance, high stability and reliability, as these are required for applications [7]. Because of their small size, low impedance and low capacitance, transient voltage suppressor (TVS) diodes are widely used for protection of electronic devices and ICs from the damage of ESD [8,9]. Moreover, the surge protectors are used for the purpose of ESD protection. The majority of electronics damage caused by transient voltage and current surges are induced by the strong electromagnetic field of power, telecommunications or radio frequency (RF) transmission lines [10]. Also, the most common causes of power surges are arise from the operation of on-off compressors and motors of high power electrical devices such as elevators, air conditioners and refrigerators [11,12].

In this study, we demonstrated new bidirectional flip chip transient voltage suppression (BD-FCTVS) devices with different Si-epi layers i.e., 6 μm and 12 μm. Process condition variations and derived structures are studied, along with a consideration of issues related to the measurement of current voltage (I-V), capacitance-voltage (C-V), ESD, transmission line pulse (TLP) and surge capability.

We found that the thin layer structure achieved low trigger voltage for improved robustness of ESD protection and reduction of the parasitic capacitance associated with diodes in the ESD protection structure. However, this also had a negative impact on the ESD characteristic of the device.

 

2. EXPERIMENTS PROCEDURE

Two BD-FCTVS devices with p+n-p+ structures were fabricated on the n+ Si (100) wafers with a resistivity of 0.002 Ω·cm. Native oxide removal was performed using HF solution. The wafers were then loaded into the reduced pressure chemical vapor deposition (RPCVD) growth chamber via a nitrogen purged loadlock chamber and the wafers were subjected to high temperature (HT) hydrogen baking at 950℃ for 5 min. A schematic of the RPCVD system (ASM Epsilon 2000 CVD system) is shown in Fig. 1. The n- Si epitaxial layers with thicknesses of 6 μm and 12 μm were then grown using the gases of silane (SiH4) and hydrogen (H2) as source gas and carrier gases, with flow rates of 30sccm and 10slm, respectively. The n- epitaxial layer growth was performed at a higher temperature of around 850℃ to 1,100℃ and the process pressure was set to 20~100 Torr. Field oxide was then grown on the epitaxial n- Si layer with high temperature oxidation baking at 1,100℃. Next, the active area windows of field oxide were opened by using the dry etching process. Two p+ regions were formed by boron implantation at energy of 80 kV with a dose of 5×1014/cm2 through a square shaped pattern of 90×120 μm2 in size of field oxide window growth on n- Si. Finally, aluminum (Al) and gold (Au) electrode metals, each with a thickness of 300 nm, were sequentially deposited on the p+ regions by using an electron beam evaporator. We measured epi layer doping concentration and thickness by using Hall measurement and scanning electron microscopy (SEM), respectively. Figure 2(a) and Fig. 2(b) shows the devices cross sectional structure and topview SEM images, respectively.

Fig. 1.RPCVD schematic diagram of ASM Epsilon 2000 CVD reactor system [13].

Fig. 2.(a) Schematic cross sectional view of BD-FCTVS device and (b) SEM images of the top view of the device.

The device’s ESD measurements were carried out using different ESD models including the machine model (MM); an ESS-2000 with a discharge gun TC-815R was used for IEC61000-4-2 standard and FNSAXII was used for the IEC61000-4-2 (IEC) standard. The TLP property was analyzed by using a Barth TLP 4002 system. During the TLP measurement, positive TLP with a standard pulse width of 100 ns and pulse rise time of 2 ns was applied to the device. The C-V measurement was under the reverse bias condition at a frequency 1 MHz performed using a precision LCR meter (Agilent 4284A) at room temperature under in a dark condition.

Surge protection measurement was carried out using a Dream 2000 for IEC61000-4-5 (ESD/surge). Parameters were extracted from surge measurements including reverse breakdown voltage, surge current, leakage current and clamp voltages. The Dream 2000 has the capability to measure maximum current up to 30 A, maximum voltage up to 60 V, and surge transient rise time at 8 μs per pulse width 20 μs (8/20 μs).

 

3. RESULTS AND DISCUSSION

The semi-log I-V characteristics of BD-FCTVS with thick epi layer diodes measured at room temperature and with various ESD characteristics including MM, and IEC stress are shown in Fig. 3(a) and Fig. 3(b), respectively. As shown in Fig. 3, the leakage current value was as low as ~ 1 nA for reverse and forward voltage ranges. These low leakage currents may ensure the strong reliability and ESD robustness of the BD-FCTVS devices [14,15]. ESD strength of the thick BD-FCTVS was extracted over ± 4 kV and ± 19 kV for MM and IEC, respectively. ESD protection device performance was measured when both the current and voltage were applied through the device while the ESD stressed, simultaneously.

Fig. 3.I-V characteristic of proposed thick BD-FCTVS wafer measured before and after: (a) MM and (b) IEC stress.

In the same way, BD-FCTVS with thin epi layer devices shows excellent ESD strength against ± 6 kV MM stress and started to increase leakage current after ± 6.5 kV as shown in Fig. 4(a). On the other hand, the IEC stress led to the negligible degradation in I-V curves as shown in Fig. 4(b) and slightly increased as the IEC peak voltage was increased, but the leakage current was still maintained below 10−9 A up to ± 29 kV stress. This implies that the BD-FCTVS device demonstrated here has sufficient leakage current margins for device application. However, ± 30 kV stress later resulted in a rapid increase in the leakage current, indicating typical electrical failures.

Fig. 4.I-V characteristics of proposed thin BD-FCTVS wafer measured before and after: (a) MM and (b) IEC stress.

Figure 5 shows the C-V measurements of both BD-FCTVS devices at 1 MHz, as shown in Fig. 5, with typical capacitance values of 15 pF and 17 pF for the thin and thick types of the two BD-FCTVS devices, respectively. Low capacitance value is beneficial in minimizing the signal attenuation at high frequency and increasing ESD protection. Moreover, when applying small voltage variations one finds that the charge is only added and removed at the edge of the depletion region such that the capacitance simply depends on the dielectric constant, the area and the depletion width. Because of the low capacitance, wider depletion width at the junction and further can be assumed to have a low electric field inside.

Fig. 5.C-V characteristic measured from the thick and thin BD-FCTVS diodes.

Figure 6(a) shows the maximum value of a surge current that can be diverted by the surge protection device. High transient surge current protection was higher for thin BD-FCTVS than thick BDFCTVS at 6 A, and 8 A. Heating problem are the major causes of device degradation and failure [16]. Fig. 6(b) shows the failure leakage current at ~ 19 V and ~ 22 V for thick and thin BD-FCTVS. The reliability of surge protection helps reduce costly downtime and protect sensitive electronic equipment against the damaging effects.

Fig. 6.ESD Surge I-V Characteristic measured of the BD-FCTVS (±8 V): (a) surge current and (b) leakage current.

Figure 7 (a) and Fig. 7(b) shows the SEM images of the damaged parts of thick and thin BD-FCTVS after ESD measurement, respectively. It found that strong damage on the device surface and the devices incurred at the pinholes surrounded by a frozen feature. This indicates that the epitaxial grown junction was severely damaged by ± 6 A of thick epi layer and ± 8 A of thin epi layers, respectively. It is clear that the surge ESD induced the metal electrode during the current flow. Under the surge measurement (Fig. 6), the junction layer breaking and the devices were created pinholes in those surface of the devices (Fig. 7) and the beneficial to minimize the clamping voltage (Vc) causes of the device failure after the surge measured.

Fig. 7.Top view SEM images of (a) thick and (b) thin BD-FCTVS diode after ESD/Surge measurement.

Finally, in order to investigate the ESD failure mechanism, real time I-V measurement was carried out using TLP analysis. As shown in Fig. 8, the devices were triggered-on at 8.5 V for the forward voltage and the clamp voltage (Vc), dynamic resistance (RD), and leakage current (IL) of the devices were extracted from I-V measurements. Figure 8(a) shows that thick device failure occurred when the TLP current reached 24.5 A and the TLP voltage increased to 50 V. In addition, the corresponding leakage current increased from ~ nA to 100 mA. However, the thin BD-FCTVS did not fail during peak pulse voltage of 750 V at 28.2 A and Vc = 33 V of the Barth electronic TLP analyzer, as shown in the Fig. 8(b). TLP analysis of thin and thick BD-FCTVS diodes shows that Vc of thin BD-FCTVS diode was reduced ~ 40% as compared with the thick BD-FCTVS. This indicates that the thin BD-FCTVS diode is better than the thick one.

Fig. 8.I-V Characteristic measured of the BD-FCTVS with (a) thick and (b) thin n- Si epi layers.

The devices had different RD and this was extracted from the linear region of the I-V curve as shown in shown in Fig. 7(a) and (b). The I-V of a diode is not constant (not a straight line) and hence the resistance cannot be measured. Due to this nonlinear nature of the curve, there exists a unique value of resistance at every point on the curve which is called dynamic resistance (not static constant resistance). The I-V of the thin device has one linear region and RD was extracted as 0.8 Ω. However, the thick device I-V curve has two regions and the corresponding values were 1.3 Ω and 1.6 Ω.

 

4. CONCLUSIONS

BD-FCTVS devices consisting of n- Si epi layers of different thickness have been developed; their electrical properties were characterized in order to evaluate ESD performance and reliability. ESD performance of BD-FCTVS diodes are strongly dependent on structure, doping concentration and dimension. Due to junctions formed in the high quality epitaxial layer, both the reverse leakage current density and the differential/dynamic resistance values could be controlled in the adequate range. The BD-FCTVS devices presented excellent ESD robustness up to ± 6.5 kV MM and ± 30 kV IEC without failure or damage. The maximum peak pulse current for the BD-FCTVS made of thin n-epi layer was measured as high as ± 8 A from a surge test and > 28.2 A from TLP measurement. Because the power and time of the surge pulse were so large, the surge I-V curves exhibited very little difference for the two DB-FCTVS devices. However, in terms of robustness, reliability, and handing power capability, the BD-FCTVS device made with a thin n- Si epi layer presented a better ESD performance than that made with a thick one. As compared with surge protection, ESD capability was more dependent upon the device structure and the dynamic resistance in response to pulses incoming at picosecond speeds.