참고문헌
- Pyoungwon Park, Jaejin Park, Hojin Park, Seonghwan Cho, "An All-Digital Clock Generator Using a Fractionally Injection-Locked Oscillator in 65nm CMOS," IEEE ISSCC Dig. Tech. Paper, pp. 336-337, 2012.
- Yongsam Moon, "A Low-Jitter Phase-Locked Loop Based on a Charge Pump Using a Current-Bypass Technique," J. Semicond. Technol. Sci., vol. 14, no. 3, pp. 331-338, June. 2014. https://doi.org/10.5573/JSTS.2014.14.3.331
- Chao-Ching Hung and Shen-Iuan Liu, "A leakage-suppression technique for phase locked systems in 65nm CMOS," IEEE ISSCC Dig. Tech. Papers, pp. 400-401, 2009.
- Yuanfeng Sun, Jun Li, Zhuo Zhang, Min Wang, Ni Xu, Hang Lv, Woogeun Rhee, Yongming Li, Zhihua Wang, "A 2.74-5.37GHz Boosted-Gain Type-I PLL with <15% Loop Filter Area," IEEE RFIC, pp. 181-184, 2012.
- Wooseok Kim, Jaejin Park, Jihyun Kim, Taeik Kim, HoJin Park, and DeogKyoon Jeong, "A 0.032mm2 3.1mW Synthesized Pixel Clock Generator with 30psrms Integrated Jitter and 10-to-630MHz DCO Tuning Range," IEEE ISSCC Dig. Tech. Paper, pp. 250-252, 2013.
-
Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa, "A
$0.032mm^2$ $780{\mu}W$ Fully Synthesizable PLL with a Current Output DAC and an Interpolative Phase Coupled Oscillator Using Edge-Injection Technique," IEEE ISSCC Dig. Tech. Paper, pp. 266-267, 2014. - Muhammad Faisal and David D. Wentzloff, "An Automatically Placed-and-Routed ADPLL for the MedRadio Band using PWM to Enhance DCO Resolution," IEEE RFIC, pp. 115-118, 2013.
- Werner Grollitsch, Roberto Nonis and Nicola Da Dalt, "A 1.4psrms-Period-Jitter TDC-Less Fractional-N Digital PLL with Digitally Controlled Ring Oscillator in 65nm CMOS," IEEE ISSCC Dig. Tech. Paper, pp. 478-479, 2010.
- Robert Bogdan Staszewski, Porast Balsara, "All-digital frequency synthesizer in deep-submicron cmos"