대한임베디드공학회논문지 (IEMEK Journal of Embedded Systems and Applications)

대한임베디드공학회 (Institute of Embedded Engineering of Korea)
권호 표지
DOI QR코드

DOI QR Code

고성능 PCM&DRAM 하이브리드 메모리 시스템

High Performance PCM&DRAM Hybrid Memory System

  • 투고 : 2016.01.29
  • 심사 : 2016.03.28
  • 발행 : 2016.04.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

In general, PCM (Phase Change Memory) is unsuitable as a main memory because it has limitations: high read/write latency and low endurance. However, the DRAM&PCM hybrid memory with the same level is one of the effective structures for a next generation main memory because it can utilize an advantage of both DRAM and PCM. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an access time and write count of PCM by using an effective page replacement. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM access count by around 60% and the PCM write count by 42% given the same PCM size, compared with Clock-DWF algorithm.

키워드

참고문헌

  1. R. F Freitas, W.W. Wilcke, "Storage- Class Memory: the Next Storage System Technology," IBM Journal of Research and Development, Vol. 52, No. 4.5, pp. 439-447, 2008. https://doi.org/10.1147/rd.524.0439
  2. G. Dhiman, R Ayoub, T. Rosing, "PDRAM: A Hybrid PRAM and DRAM Main Memory System," Proceedings of Design Automation Conference, pp. 664-669, 2009.
  3. B.S. Jung, J.H. Lee, "Analysis on the Effectiveness of the Filter Buffer for Low Power NAND Flash Memory," IEMEK J. Embed. Sys. Appl., Vol. 7, No. 4, pp. 201-207, 2012 (in Korea). https://doi.org/10.14372/IEMEK.2012.7.4.201
  4. H. Seok, Y. Pack, K.W. Park, K.H. Pack, " Efficient Page Caching Algorithm with Prediction and Migration for a Hybrid Main Memory," ACM, SIGAPP Applied Computing Review, Vol. 11, No. 4, pp. 38-48, 2011.
  5. M.K. Qureshi, V. Srinivasan, J.A. Rivers, "Scalable high performance main memory system using phase-change memory technology," Proceedings of the 36th annual international symposium on Computer architecture, pp. 24-33, 2009.
  6. S. Lee, H. Bahn, S.H. Noh, "CLOCK- DWF:A Write-History-Aware Page Replacement Algorithm for Hybrid PCM and DRAM Memory Architecture," IEEE Transactions on Computers, Vol. 63. No. 9, pp.2187-2200, 2013. https://doi.org/10.1109/TC.2013.98
  7. N. Nethercote, J. Seward, "Valgrind: A Program Supervision Framwork," Elsevier Electonc Notes in Theoretical Computer Science, Vol. 89, No. 2, pp. 44-66, 2003. https://doi.org/10.1016/S1571-0661(04)81042-9
  8. S,Eilet, M. Leinwander, G. Crisenza, "Phase Change Memory: A new memory technology to enable new memory usage models," Proceedings of IEEE International Memory Workshop, pp. 1-2, 2009.