JSTS:Journal of Semiconductor Technology and Science

  • 제16권2호
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  • Pages.185-190
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  • 2016
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Impact of Trap Position on Random Telegraph Noise in a 70-Å Nanowire Field-Effect Transistor

  • Lee, Hyunseul (Inter-universitty Semiconductor Research Center (ISRC) and School of Electrical and Computer Engineering, Seoul National University) ;
  • Cho, Karam (School of Electrical and Computer Engineering, University of Seoul) ;
  • Shin, Changhwan (School of Electrical and Computer Engineering, University of Seoul) ;
  • Shin, Hyungcheol (Inter-universitty Semiconductor Research Center (ISRC) and School of Electrical and Computer Engineering, Seoul National University)
  • 투고 : 2016.09.22
  • 심사 : 2016.01.28
  • 발행 : 2016.04.30
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초록

A 70-${\AA}$ nanowire field-effect transistor (FET) for sub-10-nm CMOS technology is designed and simulated in order to investigate the impact of an oxide trap on random telegraph noise (RTN) in the device. It is observed that the drain current fluctuation (${\Delta}I_D/I_D$) increases up to a maximum of 78 % due to the single electron trapping. In addition, the effect of various trap positions on the RTN in the nanowire FET is thoroughly analyzed at various drain and gate voltages. As the drain voltage increases, the peak point for the ${\Delta}I_D/I_D$ shifts toward the source side. The distortion in the electron carrier density and the conduction band energy when the trap is filled with an electron at various positions in the device supports these results.

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참고문헌

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