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Electronics and Telecommunications Research Institute (한국전자통신연구원)
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HV-SoP Technology for Maskless Fine-Pitch Bumping Process

  • Son, Jihye (Components & Materials Research Laboratory, ETRI) ;
  • Eom, Yong-Sung (Components & Materials Research Laboratory, ETRI) ;
  • Choi, Kwang-Seong (Components & Materials Research Laboratory, ETRI) ;
  • Lee, Haksun (Components & Materials Research Laboratory, ETRI) ;
  • Bae, Hyun-Cheol (Components & Materials Research Laboratory, ETRI) ;
  • Lee, Jin-Ho (Components & Materials Research Laboratory, ETRI)
  • Received : 2014.05.13
  • Accepted : 2015.01.17
  • Published : 2015.05.01
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Abstract

Recently, we have witnessed the gradual miniaturization of electronic devices. In miniaturized devices, flip-chip bonding has become a necessity over other bonding methods. For the electrical connections in miniaturized devices, fine-pitch solder bumping has been widely studied. In this study, high-volume solder-on-pad (HV-SoP) technology was developed using a novel maskless printing method. For the new SoP process, we used a special material called a solder bump maker (SBM). Using an SBM, which consists of resin and solder powder, uniform bumps can easily be made without a mask. To optimize the height of solder bumps, various conditions such as the mask design, oxygen concentration, and processing method are controlled. In this study, a double printing method, which is a modification of a general single printing method, is suggested. The average, maximum, and minimum obtained heights of solder bumps are $28.3{\mu}m$, $31.7{\mu}m$, and $26.3{\mu}m$, respectively. It is expected that the HV-SoP process will reduce the costs for solder bumping and will be used for electrical interconnections in fine-pitch flip-chip bonding.

Keywords

References

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