Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Efficient VLSI Architecture for Disparity Calculation based on Geodesic Support-weight

Geodesic Support-weight 기반 깊이정보 추출 알고리즘의 효율적인 VLSI 구조

  • Ryu, Donghoon (Department of Information, Communication, and Electronic Engineering, The Catholic University of Korea) ;
  • Park, Taegeun (Department of Information, Communication, and Electronic Engineering, The Catholic University of Korea)
  • 류동훈 (가톨릭대학교 정보통신전자공학부) ;
  • 박태근 (가톨릭대학교 정보통신전자공학부)
  • Received : 2015.05.27
  • Accepted : 2015.09.04
  • Published : 2015.09.25
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Abstract

Adaptive support-weight based algorithm can produce better disparity map compared to generic area-based algorithms and also can be implemented as a realtime system. In this paper, we propose a realtime system based on geodesic support-weight which performs better segmentation of objects in the window. The data scheduling is analyzed for efficient hardware design and better performance and the parallel architecture for weight update which takes the longest delay is proposed. The exponential function is efficiently designed using a simple step function by careful error analysis. The proposed architecture is designed with verilogHDL and synthesized using Donbu Hitek 0.18um standard cell library. The proposed system shows 2.22% of error rate and can run up to 260Mhz (25fps) operation frequency with 182K gates.

적응적 가중치 윈도우 알고리즘은 기존의 지역적 정합방법의 단점인 낮은 정합률을 보완하면서 전역적 방법에 비하여 실시간 하드웨어 설계가 용이하다는 장점을 갖고 있다. 본 논문에서는 객체를 분리하는데 더 유리한 지오데식 가중치 윈도우 알고리즘을 사용하여 실시간 처리가 가능한 시스템을 설계하였다. 효율적인 하드웨어 설계와 처리 효율을 높이기 위해 데이터 의존성에 따른 스케줄링을 분석하였고 계산시간이 가장 긴 가중치 계산을 기준으로 계산 단계를 최소화하여 병렬 처리를 적용하였다. 지수함수 연산은 에러분석을 기반으로 계단(step) 함수로 구현하여 하드웨어 자원을 줄이고 설계 효율을 높였다. 설계한 시스템은 verilogHDL로 설계되었으며 동부하이텍 0.18um 라이브러리를 사용하여 Synopsis를 통해 합성하였고 츠쿠바 영상을 기준으로 2.22%의 에러율과 260MHz(25fps)의 최대 동작주파수, 182K 게이트의 하드웨어 자원을 사용한다.

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