The Journal of the Korea institute of electronic communication sciences (한국전자통신학회논문지)

Korea Institute of Electronic Communication Science (한국전자통신학회)
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Measurement of Setup and Hold Time in a CMOS DFF for a Synchronizer

동기회로 설계를 위한 CMOS DFF의 준비시간과 유지시간 측정

  • 김강철 (전남대학교 전기전자통신컴퓨터공학부)
  • Received : 2015.07.27
  • Accepted : 2015.08.23
  • Published : 2015.08.31
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Abstract

As the semiconductor processing technology has been developing, multiple cores or NoC(network on chip) can be contained in recent chips. GALS(globally asychronous locally synchronous) clocking scheme that has multi-clock domains with different frequencies or phase differences is widely used to solve power consumption and clock skew in a large chip with a single clock. A synchronizer is needed to avoid a synchronization problem between sender and receiver in GALS. In this paper, the setup and hold time of DFF required to design the synchronizer are measured using 180nm CMOS processing parameters depending on temperature, supply voltage, and the size of inverter in DFF. The simulation results based on the bisection method in HSPICE show that the setup and hold time are proportional to temperature, however they are inversely proportional to supply voltage, and negative values are measured for the hold time.

반도체 공정 기술의 발전으로 하나의 칩에 많은 코어가 포함되고 있으며, 전력이나 클럭 스큐 문제들을 해결하기 위한 방안으로 다른 주파수나 위상차를 가지고 있는 여러 개의 클럭을 사용하는 GALS 기법이 사용되고 있다. GALS에서는 송수신부 사이에서 동기화 문제를 해결하기 위하여 동기회로가 사용된다. 본 논문에서는 180nm CMOS 공정 파라미터를 사용하여 온도, 전원전압, 트랜지스터의 크기에 따라 동기회로 설계에 필요한 DFF의 준비시간(setup time)과 유지시간(hold time)를 측정하였다. HSPICE의 이분법을 이용한 모의실험 결과에서 준비시간과 유지시간의 크기는 전원 전압의 크기에 반비례하고, 온도에 비례하였다. 그리고 유지시간은 음의 값으로 측정되었다.

Keywords

References

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