전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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클럭 게이팅 적용회로의 상위수준 전력 모델링

High-level Power Modeling of Clock Gated Circuits

  • 김종규 (광운대학교 컴퓨터공학과) ;
  • 이준환 (광운대학교 컴퓨터공학과)
  • Kim, Jonggyu (Dept. of Computer Engineering, Kwangwoon University) ;
  • Yi, Joonhwan (Dept. of Computer Engineering, Kwangwoon University)
  • 투고 : 2015.06.22
  • 심사 : 2015.09.30
  • 발행 : 2015.10.25
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초록

SoC (System-on-Chip) 설계초기 상위수준에서 성능뿐만 아니라 전력 분석이 중요하다. 본 논문에서는 상위수준에서 전력 분석 정확도가 높은 클럭 게이팅 구동 신호 기반 전력 모델을 제안한다. 클럭 게이팅 구동 신호의 조합으로 전력 상태를 정의하며, 클럭 게이팅 구동 신호를 자동으로 추출하여 전력 모델을 자동으로 생성할 수 있다. 실험 결과 평균 96% 이상의 정확도를 보였으며, 상위수준에서의 전력 분석 속도는 게이트 수준 대비 평균 280배 빠른 속도향상을 보였다.

Not only performance analysis but also power analysis at early design stages is important in designing a system-on-chip. We propose a power modeling based on clock gating enable signals that enables accurate power analysis at a high-level. Power state is defined as combinations of the values of the clock gating enable signals and we can extract the clock gating enable signals to generate the power model automatically. Experimental results show that the average power accuracy is about 96% and the speed gain of power analysis at the high-level power is about 280 times compared to that at the gate-level.

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참고문헌

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