An FPGA-based Fully Digital Controller for Boost PFC Converter

Abstract

This paper introduces a novel digital one cycle control (DOCC) boost power factor correction (PFC) converter. The proposed PFC converter realizes the FPGA-based DOCC control approach for single-phase PFC rectifiers without input voltage sensing or a complicated two-loop compensation design. It can also achieve a high power factor and the operation of low harmonic input current ingredients over universal loads in continuous conduction mode. The trailing triangle modulation adopted in this approach makes the acquisition of the average input current an easy process. The controller implementation is based on a boost topology power circuit with low speed, low-resolution A/D converters, and economical FPGA development board. Experimental results demonstrate that the proposed PFC rectifier can obtain a PF value of up to 0.999 and a minimum THD of at least 1.9% using a 120W prototype.

I. INTRODUCTION

Using a single-phase power factor correction (PFC) boost rectifier to improve the power factor and energy quality of an electric system is necessary according to international energy standards, such as IEC1000-3-2 [1] and IEEE-519 [2]. Boost PFC converter is the most popular among many topologies because of its simplicity and significant dynamics performance [3]. Numerous research results on the boost PFC control approach have been presented. The most widely adopted control method for boost PFC converters is the average current mode [4], [5]. Despite its many advantages, such as low harmonics input current and insensitivity to noise, the inherent drawbacks of the boost PFC converter are the complicated two-loop control and three independent voltages or currents to be measured in some applications. The one-cycle control (OCC) of boost PFC converters is proposed in [6], which introduces the nonlinear control approach with a simple structure and low cost. The benefit of nonlinear control lies in eliminating the need to sense the input voltage and in using a simple integrator to replace the complicated multiplier in the average current mode control approach. The OCC approach is widely implemented in some commercial boost PFC control microchips or solutions [7], [8]. Different modifications [9]-[11] have been reported based on the OCC method. However, applications of the conventional OCC are limited mostly to the analog field. Digital implementation boost PFC converters have attracted increasing attention in recent years. Various presented converters are based on the digital realization, modification, and extension of the average current control approach [12]-[19]. Given that the most widely reported control approach of digital PFC converters is implemented on DSP or microcontrollers, the digital realization of the average current mode control approach based on FPGA is presented in [20]. Other control methods are presented in [20]-[23]. A novel detection mechanism is proposed in [23] based on the DSP implementation for mixed conduction mode (MCM) digital controllers. A simple digital control scheme is also proposed in [23] to obtain the accurate average current in discontinuous conduction mode (DCM). Other control approaches include the precalculated duty cycle control presented in [20], [21].

As previously presented, several digital OCC approaches have been reported. The most significant obstacle to implementing OCC approach is imitating the integration part in digital implementation. An accumulator is used in [22] to calculate the sum of input current samples to obtain the average input current value. This method requires fast A/D converters and adds a heavy calculation burden to the controller in every switching cycle.

The current paper proposes an FPGA-based digital OCC (DOCC) boost PFC operating under Continuous Current Mode (CCM) condition. This boost PFC rectifier adopts the trailing triangle modulation method to capture the average input current of every switching cycle. The compensation part of the controller is designed on a new voltage loop small signal model without an explicit current loop compensation part, but results in a high power factor and low THD level over a large load range. The rest of this paper is organized as follows. Section II introduces the principle of the DOCC approach, the input current sampling method, and the system stability analysis. Section III describes the sketchy structure of the proposed controller implemented on FPGA and the criteria of system implementation issue. Section IV presents the experimental results for a 120 W boost DOCC PFC prototype. Section V concludes this paper.

 

II. ANALYSIS OF THE DOCC APPROACH

The basic objective of a PFC rectifier is to ensure that the input current is synchronized with the grid voltage (with the same frequency and phase), as shown in Fig.1. This process can be written as iL = νinGin , where iL is the average inductor current in one switching cycle, νin is the rectified grid voltage, and Gin is the emulated input admittance. Using the quasi-state approximation in the CCM boost PFC operation and assuming νin and νo are constant values in one switching cycle Ts, we obtain νo(1 - d) = νin, where d is the switching duty ratio and νo is the output voltage. The objective of the PFC controller can be expressed as follows:

Fig. 1.Boost PFC rectifier with DOCC control.

Eq. (1) indicates that the duty ratio should be applied to the switching converter in every duty cycle. Given that vin is expressed in terms of vo and d, sensing the input voltage is unnecessary. vo is sampled by a low-cost A/D converter. Gin is computed by the compensation part of the voltage loop, which will be analyzed in a detailed derivation in the following sections. The most tricky problem is the acquisition of the average current of the duty cycle. Four basic current sample methods (i.e., trailing edge mode, leading edge mode, trailing triangle mode, and leading triangle mode) are used in a switching power system, as shown in Fig. 2. Triangle modulation is adopted in the DOCC current sampling operation method because trailing edge modulation or leading edge modulation is unsuitable in average current acquisition. Given that the rectifier can enter the DCM mode, the current at the Ts/2 instant can be difficult to track and sample. Hence, the trailing triangle modulation is utilized for the prototype design in this paper.

Fig. 2.Sketch map of the pulse width modulation (PWM) types. (a) Trailing edge modulation. (b) Leading edge modulation. (c) Trailing triangle modulation. (d) Leading triangle modulation.

Fig. 2 shows that the power switch is always turned on at the beginning of every switching cycle, but is turned off at the dTs/2 instant. The switch is not turned on until the (1˗d/2)Ts instant. The sample current iL[n˗1] at an instant is the average current of the (n˗1)th switching cycle. The quasi-state approximation shows that the switching frequency is much faster than the input current frequency. Thus, we can take the sample average current iL[n˗1] at an instant as the average current criterion iL[n] in the nth switching cycle by assuming two consecutive switching cycles with the same average current. This approximation can provide significant convenience in control analysis and system implementation.

Adopting the trailing triangle modulation for average current iL[n] acquisition has the following primary merits. 1) The average current of the switching cycle is obtained through a relatively simple method without the need for an accumulator [22]. This condition can save on hardware consumption in FPGA implementation. The current sampled at a fixed instant on the switching frequency makes the utilization of low-cost and low-speed A/D converters possible. It also makes the design of sampling circuit easy. 2) The average current criterion is acquired at the beginning of the switching cycle. This approach leaves sufficient time to calculate the appropriate duty ratio for the switching cycle online.

Assuming that the input current is higher than the criterion value by some disturbance or other interference, the acquired average current is also higher. The duty ratio of the following switching cycle is lower than the normal level to correct the input current to the normal level based on Eq. (1). When the input current is lower than the normal level, the opposite process is implemented to correct it. This mechanism guarantees that the fluctuation of input current does not influence the system stability.

Fig. 3.Input current sample operation with trailing triangle modulation.

Fig. 4.Root locus plot of Ti(z) for implementation on the proposed DOCC PFC controller.

The small signal stability of control law (Eq. 1) can be analyzed based on the quasi-state approximation from another perspective. The current loop compensation transfer function is expressed in the discrete domain as follows:

In one switching cycle

The linearization of Eq. (3) yields the duty ratio to current transfer function as follows:

The discrete time current open loop transfer function is obtained in Eq. (5) by combining Eq. (2), Eq. (4), and the input current sampling coefficient KiL. The sketch map of the current loop is shown in Fig. 5(a).

Fig. 5.Sketch maps. (a) Current-loop structure. (b) Voltage-loop structure.

The root locus technique in Fig. 4 shows that the current loop is stable when the parameter Gk = KiLTs/GinL < 1, whereas the condition that guarantees the boost PFC converter that operates in CCM is Gc = Ts/GinL < 1 [24]. Fig. 6 illustrates the CCM, DCM, and MCM current operating modes for boost PFC converters. We can conclude that the current loop of the DOCC boost PFC rectifier is always stable without any explicit compensation part when it always operates in the CCM condition [24]. The current rectifier loop is still possibly stable (Gk < 1) because the current sampling gain KiL is generally less than 1 when the DOCC boost PFC operates in MCM or DCM (Gc > 1).

Fig. 6.Illustration of the PFC operating in CCM, DCM, and MCM.

The emulated input admittance Gin can be obtained through an analysis of the system voltage loop, as shown in Fig. 5(b). Although most analyses of the nonlinear-control boost PFC is based on the small signal introduced in [24], the current study simplifies the analysis by assuming that the power system efficiency closely approximates 1. Thus,

The Vinrms in Eq. (5) represents the root mean square (RMS) value of input voltage vin, Iinrms represents the RMS value of the input current, and io denotes the output current of the system. Fig. 6 can be expressed as follows:

Iinref denotes the RMS value of the input reference current, and Kvo is the output voltage sampling coefficient. Combining Eqs. (6) and (7) results in the following:

The following equation is obtained when the disturbance to Eq. (8) is added:

We then obtain the following after the small signal analysis of Eq. (9):

The output current can be expressed as follows:

The small signal expression of Eq. (10) is as follows:

Combining Eqs. (10) and (12), the small signal relationship between vo and Gin, after the discretization of the transfer function by the zero-order hold method is obtained in Eq. (13), where Tss represents the sampling time of the discretization process.

Designing a stable feedback voltage loop is necessary to respond to the load variation, parameter offset of power devices, and input voltage Vinrms fluctuation. A tradeoff exists between the output voltage dynamics performance and limited loop bandwidth in this part. The proportion-integration compensation part Gvc is used in this study to set the crossover frequency of the voltage loop at approximately 20 Hz (with a 60° phase margin) to suppress the second harmonics of the output voltage while guaranteeing the required voltage-loop dynamics performance. The compensated voltage loop gain and phase margin are shown in Fig. 7.

Fig. 7.Closed voltage-loop gains Tv(z) with the Gvc compensation scheme.

 

III. IMPLEMENTATION ISSUES

Determining the switching frequency fs is dependent on specific application circumstances. A high switching frequency generally means a low output voltage ripple level under the same capacitor and inductor condition. A more serious electromagnetic interference problem also occurs, which causes lower system efficiency. We set the switching frequency at approximately 50 kHz after the tradeoff process. The switching period being the integer multiples of the controller clock period is simpler for the design of the digital PWM (DPWM) function. Thus, we determine fs = 48.8 kHz in this prototype implementation.

The input inductor value affects the ripple level of the input current, as well as the current operating mode of the system shown in Fig. 8. Eq. (1) shows that the entire control system is based on the assumption that the rectifier operates in the CCM mode. Eq. (14) divides the CCM and MCM regions as obtained from [24]. It determines the minimum inductor value for the CCM operation. Eq. (15) divides the DCM and MCM regions. We represent the boundaries between CCM, MCM, and DCM over load variation in Fig. 8 while maintaining the input voltage Vinrms (50 V), switching frequency fs (48.8 kHz), and output voltage Vo (80 V) constant.

Fig. 8.Illustration of the boost PFC operating in different modes.

The inductor L should satisfy the following relation to guarantee the continuous input current during the operation:

We obtain L > 420 μH with Pmax = 128W, Vinmax = 71.7 V, Iinmax = 3.6 A, and fs = 97.6 kHz. We then take L = 500 μH with a certain safety margin.

Fig. 9.Diagram of the proposed PFC controller scheme.

The value of the output capacitor C2 is calculated according to its hold time Δt. Hold time expresses the time duration for the capacitor voltage hold in a prescribed range without any of the power source income. The said value can be expressed based on the law of conservation of energy:

The output voltage ripple should generally be σ < 5%. Given that the reference output voltage is Vo = 80 V, Vomax = 84 V and Vomin = 76 V are obtained. In this study, the output capacitor value is calculated as 1000 μF when the hold time Δt is set as 5 ms.

The controller implementation based on FPGA can achieve multi-model system integration with few peripheral devices and routings. The parallel computing character of FPGA can also guarantee the real-time requirement of several complex algorithms.

Table I lists the parameters of the proposed boost PFC prototype. We only utilize the upper eight-bit digital output of the selected A/D converter LTC1412. The MSB of the digital output indicates the output value sign. Thus, the output range of LTC1412 is ˗2.5 V to 2.5 V, and the gain of the selected A/D converters is Kad = 27/2.5 ≈ 51. Fig. 1 and Table I show that the gain of the output voltage divider network that consists of R1 and R2 is Kvo = 0.025, and the output voltage amplification coefficient is Kav =1. The equivalent coefficient of the output voltage sampling part is Kvoe = KadKvoKav= 1.275. With the same principle (i.e., the sampling resistor R3 = 0.1 Ω, input current amplification coefficient Kai = 5, and gain of the sampling resistance is set at KiL = 0.5), we obtain the equivalent gain of input current sampling part KiLe = KadKiLKai = 25.5.

TABLE ICONVERTER SPECIFICATIONS

Fig. 10 illustrates the experiment set-up of the proposed boost PFC rectifier. An isolating transformer with a transformer ratio of 1:1 is used for safety consideration. Vinrms = 50 V is obtained by the voltage regulator. We use the IT8514 DC electronic load to generate the system load and load step. The PF and THD are measured by a WT210 digital power meter. The equivalent emulated input admittance Gine[n] is the indicator of load condition for the proposed prototype in Fig. 11. Gine[n] can be used to assess the load condition and judge the load variation. In this study, the value range of Gine[n] is approximately 500 to 800 for an optimal boost PFC performance. Gine[n] < 500 indicates that the PFC rectifier enters the MCM/DCM. Eq. (14) divides the CCM and MCM regions [24], whereas Eq. (15) divides the DCM and MCM regions. Fig. 11(a) shows that the PF significantly decreases because the entire control system is based on the assumption that the rectifier operates in the CCM mode. The system THD descends when Gine[n] < 500 because the harmonics current proportion increases as shown in Fig. 11(b). Fig. 11(c) shows the relation between emulated input admittance Gine[n] and output power P under different inductor values.

Fig. 10.Photo of the experiment set-up for the proposed boost PFC.

Fig. 11.Proposed digital controller performance with input inductor. (a) Power factor. (b) THD, and (c) Gine[n].

 

IV. EXPERIMENTAL RESULTS

Fig. 12 shows the PWM waveform (upper, ch1) and conversion signal waveform (under, ch2). The falling edge of the conversion signal waveform triggers the input current sampling process instantaneously. The input current is always sampled at a fixed instant on the switching frequency.

Fig. 12.DPWM and conversion signal waveform.

Fig. 13 shows the input voltage waveform (upper, ch2) and average input current waveform (under, ch1) after the proposed PFC that operates in a 120Wload. The average input current is perfectly synchronized with the input voltage.

Fig. 13.Input current and voltage waveform with PFC.

Fig. 14 shows the input current envelope captured by the hall current sensor at a 120 W load. Fig. 15 is the input current waveform at a 40 W load. As previously analyzed, the PFC rectifier enters the MCM/DCM mode.

Fig. 14.Input current envelope waveform in a 120 W load.

Fig. 15.Input current envelope waveform in a 40 W load.

Fig. 16 shows the waveform of the input current captured at sampling resistance R3 (under, ch3) and input voltage waveform (upper, ch1) at a 120 W load. The system always operates in CCM under this load level.

Fig. 16.Input current waveform in a 120 W load.

Fig. 17 show the waveform of the input current captured at sampling resistance R3 (under, ch3) and input voltage waveform (upper, ch1) at a 40 W load. The system operates in CCM when the input voltage is near the peak value of the rectified cycle, whereas it operates in DCM when the input voltage is near the minimum value. This scenario indicates that the system enters the MCM under this load level, which results in a high harmonics level and low PF value (Fig. 11).

Fig. 17.Input current waveform in a 40 W load.

We exhibit the output voltage vo waveforms to verify the validity of the voltage loop. Fig. 18 shows the output voltage regulation process from 120 W to 64 W load step. The said figure shows that the maximum overshoot output voltage is Voo = 92.5 V, and the system takes approximately 1360 ms to regulate the voltage to steady state (80 V). Fig. 19 shows the output voltage regulation process from the 64 W to 120 W load step, which is the reverse process of the load step in Fig. 4. The output voltage elapses by 825 ms before it recovers to 80 V, and the minimum undershoot output voltage is Vou = 68.2 V. Notably, the system takes a longer regulation time to return to stability when the load step is from 120 W to 64 W compared with reverse load step process from 64 W to 120 W. This scenario is the typical phenomenon for single-ended boost topology because it has no energy release path in the load drop step process.

Fig. 18.Output voltage regulation from 120 W to 64 W load step.

Fig. 19.Output voltage regulation from 64 W to 120 W load step.

 

V. CONCLUSION

This paper presents an FPGA-based fully digital controller for boost PFC converters. The proposed PFC converter realizes the DOCC control approach, which requires no input voltage sensing, two-loop compensation part design, or complicated average current sampling and calculation process. It obtains a high power factor and the operation of low harmonic input current ingredients over a large load range under CCM. Implementation of the proposed PFC system and structure of the FPFA-based controller are discussed in detail. Experimental results demonstrate that the proposed PFC rectifier can obtain a PF value of up to 0.999, and the minimum THD decreases to 1.9% by a 120 W prototype that operates in 50 V input line voltage. The feasibility and suitable dynamics response under variable load conditions of the proposed prototype are satisfactory.