An Inherent Zero-Voltage and Zero-Current-Switching Full-Bridge Converter with No Additional Auxiliary Circuits

Abstract

An inherent zero-voltage and zero-current-switching phase-shifted full-bridge converter with reverse-blocking insulated-gate bipolar transistor (IGBT) or non-punch-through IGBT is proposed in this paper. This converter not only ensures that the switches in the lagging leg works at zero-current switching, but also minimizes circulating conduction loss without any additional auxiliary circuits. A 1.2 kW hardware prototype is designed, fabricated, and tested to verify the proposed topology. The control loop design procedures with small-signal models are also presented. A simple, low-cost, and robust democratic current-sharing circuit is also introduced and verified in this study. The proposed converter is a suitable alternative for compact, cost-effective applications with high-voltage input.

I. INTRODUCTION

Galvanic isolated full-bridge (FB) converter is the standard topology in medium- and high-power applications, such as telecom power supplies, X-ray generators, electrical vehicles, and traction applications [1]-[4]. The main concerns in these fields are reliability, efficiency, power density, cost, and other specific specifications (e.g., wide soft-switching range, low topology-complexity, small circulating current, and minimized duty cycle loss) [1]-[3]. Three converter types can fulfill these demands: resonant FB [3], phase-shift pulse-width-modulated (PS PWM) FB [1], and hybrid resonant and PS PWM FB converters [5], [6].

Resonant circuit topologies, especially variable frequency LLC converters, have become popular in recent years. The major advantages of these topologies are zero-voltage switching (ZVS) or zero-voltage transition and nearly zero-current switching (ZCS) for primary switches, ZCS for output diodes, and eliminated output choke. In addition, a wide range of soft switching is achieved even with no-load condition. However, the extremely high runaway frequency at no-load or short-circuit condition is a potential threat to system reliability.

Alternatively, additional series inductors are often inserted but can be bulky with more duty cycle loss and circulating current to extend the ZVS range of the classic constant-frequency PS PWM FB converters [1]-[4]. Hybrid resonant and PS PWM FB converters significantly lower series inductance with true full-range soft switching and negligible duty cycle loss features [5], [6]. These converters are suitable candidates for electric vehicle chargers at the cost of complicated structures and control strategies.

High-voltage insulated-gate bipolar transistors (IGBTs) with constant voltage drop are often preferred in three-phase 380 Vac/440 Vac or 750 Vdc/1500 Vdc input systems. A series of zero-voltage and zero-current-switching (ZVZCS) techniques has been proposed to solve the IGBT tail current issue in the lagging leg (e.g., primary impedance blocking, primary resetting, secondary voltage clamping, and output voltage resetting) [7]-[12]. These auxiliary circuits are almost inevitable, and negative effects should also be considered (e.g., steady-state primary current overshoot and additional high-voltage stress of the rectifier during the start-up period).

These techniques were recently reviewed and reexamined to achieve the balance between performance and cost with novel commercial SiC and Si devices [13], [14]. Complex three-level FB converters that use low-voltage MOSFETs are another possible solution [15]. New high-speed generations of IGBTs have already been recognized as a cost-effective alternative to super junction MOSFETs in zero-voltage transition PS FB high-voltage to low-voltage DC/DC converters. The capacitive snubber or resonant inductor can be optimized for particular operating points, but not for required wide operating ranges as shown in [14]. Measures to improve the efficiency must be carefully selected to avoid conditions wherein a loss mechanism is lowered or partly avoided, whereas others are unintentionally increased, thus canceling the expected benefits. The analysis in [14] also shows that the best converter efficiency can be achieved without additional components in the case of IGBT_H3.

Among these next-generation IGBTs, Reverse-Blocking (RB) IGBTs have been investigated and tested in current-source inverters, resonant inverters, T-type neutral-point-clamped converters, and matrix AC/AC choppers. RB IGBTs offer more advantages over functionally comparable conventional circuits, such as loss reduction, compact structure, and lower cost [16]-[22].

The present study attempts to determine a low topology-complexity ZVZCS PS PWM FB converter with few negative effects for high-input voltage application. A novel, inherent ZVZCS PS PWM FB converter without additional auxiliary circuits is also proposed, described, designed, and tested. The proposed converter can achieve ZCS for lagging-leg switches without a circulating current with the help of RB IGBT or non-punch-through IGBT with RB feature.

 

II. BASIC OPERATION PRINCIPLE OF THE NOVEL CONVERTER

Fig. 1 illustrates the circuit diagram of the proposed inherent ZVZCS PS PWM FB converter, which consists of the following four parts:

Fig. 1.Circuit diagram of the proposed inherent ZVZCS PS PWM FB converter.

No additional auxiliary ZVZCS circuits are used in the circuit.

The topology operation principles can also be explained by the gate sequences and associated key voltage and current waveforms illustrated in Figs. 1 and 2, where Cs1 and Cs2 are the equivalent capacitance of the IGBTs S1 and S2 respectively, vge_lag and vge_lead are the IGBT drive signals respectively, Vin is the input voltage, V0 is the output voltage, vAB is FB leg middle-point voltage, vc is the voltage across the blocking capacitor CB, vrec is the rectifying voltage before the output filter, iP is the main transformer, Tr is the primary current, IL is the current through the choke Lf, Deff is the effective duty ratio, and Ts is the switching period.

Fig. 2.Key operation waveforms of the proposed converter.

The topology in the half PWM cycle has six distinct operation modes, as shown Fig. 3. Similar operation principles in the second half PWM cycle are not provided because of the symmetric circuit structure. The following assumptions are made at this point to simplify the analysis.

Fig. 3.Operation modes of the proposed converter.

Mode [t0–t1] [Fig. 3(a)]: S1 and S4 conduct while S2 and S3 are both deactivated. The input power is delivered from the primary to the output. The primary current ip = IL/n charges the blocking capacitor CB at the same time, where n is the main transformer primary-to-secondary ratio.

Mode [t1–t2] [Fig. 3(b)]: S1 is turned off, whereas S4 conducts at t1. The primary ip (i.e., reflected load current to the primary) charges Cs1 and discharges Cs2 linearly. The capacitors provide the ZVS condition for S1 as follows:

Mode [t2–t3] [Fig. 3(c)]: The primary ip fully discharges Cs2 at t2, and the body or external diode DS2 of S2 is naturally turned on. Thus, S2 can turn on at the zero-voltage condition during this interval.

vAB is clamped to zero because of the simultaneous conducting of DS2 and S4. Therefore, the blocking capacitor voltage vc decreases the primary current ip.

Given that the reflected secondary ip cannot supply the constant inductor current iL, the secondary rectifier diodes D1 and D2 both conduct for the freewheeling iL.

Mode [t3–t4] [Fig. 3(d)]: The primary current reaches zero at t3. Given the RB IGBT, S4 does not provide ip the reverse current path, ip is maintained at zero state during this interval, and a circulating current state occurs for the conventional ZVS PS FB. The zero state also provides the ZCS condition for S4 to be turned off.

The rectifier diodes D1 and D2 still conduct and share the load current in the secondary circuit.

Mode [t4–t5] [Fig. 3(e)]: S4 is turned off at the zero-current condition at t4. After a short delay of dead time, S3 can turn on at t5.

Mode [t5–t6] [Fig. 3(f)]: S3 is turned on by the PWM command at t5. S3 is turned on at the zero-current condition because of the leakage inductor Llk that limits the increase in primary current ip at the negative direction.

The increasing primary current ip cannot supply the load current during this interval, and both secondary rectifier diodes conduct, which clamps the voltage across the transformer windings at zero.

The primary current ip reaches the reflected load current to the primary at t6, and the input voltage source starts to deliver power from the primary to the output such that the second half-cycle starts at t0.

 

III. DESIGN CONSIDERATIONS

A. ZVS Range of the Leading Leg

The ZVS transition of the leading- leg is supported by the secondary side filter inductance Lf and the transformer leakage inductance Llk. Thus, the ZVS range of the leading- leg is relatively wide but only limited at light loads, as illustrated below:

B. ZCS Range of the Lagging Leg

The ZCS transition of the lagging- leg is determined as [t2, t3] and [t3, t4], as shown in Fig. 2, where the primary current must decrease to zero before the PWM signal is applied to the IGBT in the lagging- leg at t23.

Consider the following:

where Deff is defined as the effective duty ratio shown in Fig. 2, and Ts is the switching period. Thus, Eq. (3) can be revised as follows:

This condition indicates that t23 is independent of the load current and is inversely proportional to Deff. With sufficient Deff that to fulfills the output voltage regulation, the ZCS transition of the lagging- leg can be achieved in the total line input and output load range, including the no -load condition.

C. Circulating Current Elimination

Mode [t3–t4] and Fig. 2 show that the primary current reaches zero at t3 and remains at zero because of the adopted RB IGBTs in the lagging leg, which do not provide ip to the reverse current path. Therefore, the circulating current does not exit and helps the efficiency improvement.

D. IGBT Selection in the Lagging Leg

Currently, the primary manufacturers of RB IGBTs are Fuji, IXYS, Mitsubishi, and Infineon. These manufacturers all have their own design, so the RB-IGBT architecture depends on the manufacturer. The architecture of an RB-IGBT from IXYS is described in [24]. This company modified an NPT-IGBT by using isolation diffusion and folding up the lower p+ layer at the chip edge, as shown in Fig. 4. Performing the p+-n˗ junction that blocks the reverse voltage prevents breakthrough at the chip edge. The p+-n˗ junction continues to the isolation layer at the gate connection. These modifications enable the IGBT to block negative collector-emitter voltages as a normal p-n diode and still have the operational behavior of a normal NPT-IGBT. The maximum RB voltage for this device is 1200 V.

Fig. 4.Architecture of an non-punch-through(NPT) IGBT (left) and IXYS (right). RB-IGBT with an intrinsic diode (right).

Given the limited RB-IGBTs provided in the manufacturers’ product category, mass production and cost issues are also concerns for the proposed novel FB converter. The detailed architecture of an IGBT is reexamined at this point. The body-drift region junction in Fig. 5 is the junction that blocks the forward voltage when the device is off, and the junction between the p+ injection and n˗ layers is the junction that blocks the reverse voltage. Thus, the NPT-IGBT can theoretically block a reverse voltage as high as the magnitude of the forward voltage. The NPT-IGBT without a body diode is a possible low-cost solution to replace the RB-IGBT for mass production. The optimization of switching performance of the RB-IGBT is no longer a key issue that makes the RB IGBT still relatively unacceptable in real applications [23]. Common IGBT drivers are sufficient, and the prototype only uses a small driver transformer to drive the NPT-IGBT.

Fig. 5.Detailed architecture of an IGBT.

E. Current Sharing Strategy with Multiple Modules

The paralleling of standardized converter modules generally offers several advantages, such as redundancy implementation, expandability of output power, and ease of maintenance. When multi-converter modules operate in parallel, the major issue is load-current sharing among the different modules [25]. Among the different approaches, the democratic current-sharing method is preferred for its autonomous current-sharing feature. A simple, low-cost, and robust democratic current-sharing circuit is introduced at this point with diodes, as shown in Fig. 6. The connecting current bus after the maximum value detection circuit forces the current reference to be the same, which follows the maximum value of the different voltage loop output. The different inner current loop further regulates the module output current independently.

Fig. 6.Current-sharing circuit.

 

IV. CONTROL LOOP DESIGN FOR VOLTAGE AND CURRENT REGULATIONS

The proposed ZVZCS FB converter is used as a downstream main circuit of a marine lead-acid battery charger whose front-end converter is a three-phase passive rectifier. The constant current (CC) and constant voltage (CV) charge modes are preferred for a lead-acid battery [26]. Therefore, the control loops for the voltage and current regulations should be carefully designed [27], [28].

The battery model is complicated because of its electrochemical feature under charge/discharge management. One approach is to model the battery as an equivalent resistor in charging mode, while another approach models the battery as a DC source with its series resistor. Major loop design differences between these models occur at the low-frequency stage. Key factors such as crossover frequency are unaffected [29]. Consider that an electronic load-based battery emulator is used in this study for convenience. Thus, the lead-acid battery is modeled as an equivalent resistor.

Finally, the real lead-acid battery is further used to reexamine the controller.

Fig. 7 illustrates that several small-signal transfer functions are defined as follows:

Current loop gain before compensation:

Current loop gain after compensation:

Modulator can be modeled by a constant gain:

where Vpp = 2.35 V is the peak-to-peak voltage of the triangular carrier signal.

Fig. 7.Control loop block.

Gvd(s) is the duty-ratio-to-output-voltage transfer function.

GiLd(s) is the duty-ratio-to-inductor-current transfer function shown in Eq. (12):

Gi(s) is the inner-loop compensation gain:

Gv(s) is the outer-loop compensation gain:

Kv(s) = 0.1 is the output voltage sense gain, Ki(s) = 0.1 is the current sense gain, D is the FB converter duty ratio, Lf is the inductance, C0 is the output capacitor, R is the load resistance, RC is the equivalent series resistance of the output capacitor, and RL is the equivalent series resistance of the inductor in these transfer functions.

We selected the current loop crossover frequency after compensation fci = 0.1˗0.2fs in these transfer functions. We then placed the zero fz1 of Gi(s) at the output resonance frequency f0 for damping and pole fp1 = fs/10 for switching ripple elimination.

At this point, the current loop gain magnitude at fci before compensation is ｜Ti_o1(j·2πfc)｜dB , which indicates that the compensation gain should be as follows:

which ensures that the current loop gain magnitude at fci after compensation is zero.

Furthermore,

Considering the component tolerances, the resistors and capacitors whose values are near the calculated ones are selected and then reexamined by the Bode plots, as shown in Fig. 8. The current loop crossover frequency is fci = 2.9 kHz, and the phase margin is 40°, which means that the current loop has a suitable stable and dynamic performance.

Fig. 8.Loop gains after compensation.

After the current loop is closed, the inner loop is used as a power stage as follows:

The outer loop gain before compensation is as follows:

The outer loop controller and outer loop gain can be designed similar to the previously mentioned gains. The outer loop gain after compensation is described as shown in Eq. (21), and more information is provided in Fig. 8.

(current loop cross over frequency fci = 2.9 kHz, PM = 40°, R4 = R5 = 10 kΩ, R6 = 6.2 kΩ, C3 = 47 nF, C4 = 13 nF; outerloop crossover frequency fcv = 390 Hz, PM = 80°, R1 = R2 = 10 kΩ, R3 = 30 kΩ, C1 = 9.1 nF, C2 = 2.7 nF)

 

V. EXPERIMENTAL VERIFICATION

A. Hardware Description

A 1.2 kW hardware prototype for a marine battery charger was designed, fabricated, and tested to verify the proposed converter and current-sharing strategy. The final charger product started its type test. Detailed specifications and parameters are shown in Fig. 9 and Table I. A single-chip Atmega64 controller provides the voltage and current reference for battery charge management, while a TI UCC3895 IC controls the FB circuit.

Fig. 9.Prototype photograph. (a) 3D view of the virtual prototype. (b) Interior of the actual prototype.

TABLE IOPERATION CONDITIONS AND CIRCUIT PARAMETERS

B. Experimental Key Waveforms

Fig. 10 provides the detailed experimental results of the topology shown in Fig. 2. The fast reset of the primary current is observed in Fig. 10(a), which implies that the circulating current is eliminated, thus helping in efficiency improvement.

Fig. 10.Experimental results.

Fig. 10(b) illustrates the FB primary middle-point voltage and transformer primary voltage. The difference between the voltage drops in the blocking capacitor CB is shown in Fig. 10(c).

Fig. 10(d) shows the ZCS operation of the IGBTs in the lagging leg with load current adaptability. Notably, the device current drops to zero at the light-load condition before the gate signal is turned off. Thus, the ZCS is achieved at this point, although the ZVS condition of the lagging leg is still not obtained as shown in Fig. 10(e). Fig. 10(f) shows the test using the simple phase-shift modulation method.

C. Experimental Data and Discussion

Fig. 11 further provides the efficiency curve of the prototype. The expected high efficiency is guaranteed because of the topology with intrinsic soft switching and eliminated circulating current features. The maximum efficiency is approximately 93% under 540 Vdc input and 28 Vdc output condition, where auxiliary power and fan losses are also included.

Fig. 11.Efficiency curve.

The decrease in efficiency for currents of 30 A up to 40 A is caused by conduction losses, especially the output rectifying diodes. The impact of conduction losses is highly significant in converters with low output voltage and high output current, such as in our case. In addition, no energy recovery circuits are added in the converter to clamp rectify diode voltage spikes and to achieve forward and reverse recovery current optimization.

Nevertheless, the efficiency is relatively high, unlike the ZVS FB converter in Fig. 11. The only differences between these converters are that the IGBTs without body diodes in the lagging leg use the same devices with body diodes in the leading leg. High-output voltage and low-output current will be higher, especially in the case where the synchronous rectification technique or lossless energy recovery clamp circuits are introduced [30].

Fig. 12 shows the hot-spot temperature curves of the prototype devices. Thermal balance is achieved after 30 min of work. The maximum temperature increase is approximately 20 ℃ for primary switches and secondary diodes. The hottest component is the output choke, which is insensitive to the heat.

Fig. 12.Prototype devices with hot-spot temperature curves (ambient temperature: 25 ℃).

Table II further summarizes the current distribution for a parallel connection of two prototype modules. The current-sharing accuracy is in the 1% to 6% range in the entire load range with the current-sharing bus connected. Even at a light-load condition, the current distribution is insensitive to the noise. The error is mainly caused by the mismatching in circuit power stages because the sharing bus provides the same DC current reference. The implementation of the true N + 1 redundant system can then be conducted [25].

TABLE IIDATA OF PARALLEL CURRENT SHARING

Table III further provides a comparative study of the possible prototype candidates. The proposed topology exhibits a suitable balance between performance and cost for industry application with the least components and devices in different possibilities.

TABLE IIIEVALUATION CONDITIONS AND RESULTS

 

VI. CONCLUSIONS

A novel inherent ZVZCS PS FB converter is proposed in this paper. The operation principles, specific design considerations, and experimental results are presented. The distinctive features of the proposed topology are summarized as follows.