IEMEK Journal of Embedded Systems and Applications (대한임베디드공학회논문지)

Institute of Embedded Engineering of Korea (대한임베디드공학회)
권호 표지
DOI QR코드

DOI QR Code

New Embedded Memory System for IoT

사물인터넷을 위한 새로운 임베디드 메모리 시스템

  • Received : 2015.03.06
  • Accepted : 2015.05.22
  • Published : 2015.06.30
Download PDF
⟨ Previous Next ⟩

Abstract

Recently, an embedded flash memory has been widely used for the Internet of Things(IoT). Due to its nonvolatility, economical feasibility, stability, low power usage, and fast speed. With respect to power consumption, the embedded memory system must consider the most significant design factor. The objective of this research is to design high performance and low power NAND flash memory architecture including a dual buffer as a replacement for NOR flash. Simulation shows that the proposed NAND flash system can achieve better performance than a conventional NOR flash memory. Furthermore, the average memory access time of the proposed system is better that of other buffer systems with three times more space. The use of a small buffer results in a significant reduction in power consumption.

Keywords

References

  1. http://download.intel.com/newsroom/kits/ces/2015/pdfs /Intel_CURIE_Module_Factsheet.pdf
  2. H. Sian, "Rethinking memory design for IoT and wearables," EE Times-Asia, 2014.
  3. Micron Technology, "Memory Solutions for the Internet of Things (IoT) Convergence," 2014, Internet access http://www.arrowglobalvillage.fi/media/arrow_micron-iot-convergence-emea-may-2014-rev1.pdf
  4. T. Benavides, J. Treon, J. Hulbert, W. Chang, "The Enabling of an Execute-In-Place Architecture to Reduce the Embedded System Memory Footprint and Boot Time," Journal of Computers, Vol. 3, No. 1, pp. 79-89, 2008.
  5. S. Park, J. Park, S. Kim, "Short-Random Request Absorbing Structure with Volatile DRAM Buffer and Nonvolatile NAND Flash Memory," Proceedings the 3rd WSEAS International Conference on Computer Engineering and Applications, pp. 257-262, 2009.
  6. Toshiba, "NAND vs. NOR Flash Memory Technology Overview," Internet access http://umcs.maine.edu/-cmeadow/courses/cos335/Toshiba%20NAND_vs_NOR_Flash_Memory_Technology_Overviewt.pdf.
  7. J. Zhao, H. Wu, Y. Zhao, W. Liu, "CCM: Low cost dynamic data exchange to emulate RAM on NAND flash," Proceedings of 20th Embedded and Real-Time Computing Systems and Applications, pp. 1-9, 2014.
  8. http://cache.freescale.com/files/microcontrollers/doc/fact_sheet/KINETISKL03CSPFS.pdf
  9. C. Park, J. Seo, S. Bae, H. Kim, S. Kim, B. Kim, "A low-cost memory architecture with NAND XIP for mobile embedded systems," Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/software codesign and system synthesis, pp. 138-143, 2003.
  10. N.P. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully Associative Cache and Prefetch Buffers," Proceedings of the 17th Annual International Symposium on Computer Architecture, pp. 364-373, 1990.
  11. Y.H. Lee, S.S. Lim, "Worst Case Response Time Analysis for Demand Paging on Flash Memory," Journal of the Korea Society of Computer and Information, Vol. 12, No. 6, pp. 113-123, 2006 (in Korea).
  12. W.T. Huang, C.T. Chen, C.H. Chen, C.C. Chen, "Energy-Efficient Buffer Architecture of Flash Memory," Proceedings of International Conference on Multimedia and Ubiquitous Engineering, pp. 543-546, 2008.
  13. http://euler.slu.edu/-fritts/mediabench/
  14. D. Burger, T. Austin, "The SimpleScalar tool set, version 3.0," University of Wisconsin-Madison, 2011.
  15. H. Nazarian, "Storage Systems Incorporating RRAM Technology," Proceedings of Flash Memory Summit, pp. 1-16, 2013.