Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

Extraction of Average Interface Trap Density using Capacitance-Voltage Characteristic at SiGe p-FinFET and Verification using Terman's Method

SiGe p-FinFET의 C-V 특성을 이용한 평균 계면 결함 밀도 추출과 Terman의 방법을 이용한 검증

  • Kim, Hyunsoo (School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Seo, Youngsoo (School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Shin, Hyungcheol (School of Electrical Engineering and Computer Science, Seoul National University)
  • 김현수 (서울대학교 전기.정보공학부) ;
  • 서영수 (서울대학교 전기.정보공학부) ;
  • 신형철 (서울대학교 전기.정보공학부)
  • Received : 2014.12.11
  • Accepted : 2015.03.30
  • Published : 2015.04.25
Download PDF
⟨ Previous Next ⟩

Abstract

Ideal and stretch-out C-V curve were shown at high frequency using SiGe p-FinFET simulation. Average interface trap density can be extracted by the difference of voltage axis on ideal and stretch-out C-V curve. Also, interface trap density(Dit) was extracted by Terman's method that uses the same stretch-out of C-V curve with interface trap characteristic, and average interface trap density was calculated at same energy level. Comparing the average interface trap density, which was found by method using difference of voltage, with Terman's method, it was verified that the two methods almost had the same average interface trap density.

고주파에서 이상적인 커패시턴스-전압 곡선과 결함이 존재하여 늘어진 커패시턴스-전압 곡선을 SiGe p-FinFET 시뮬레이션을 이용하여 보였다. 두 곡선이 게이트 전압 축으로 늘어진 전압 차이를 이용하여 평균적인 계면 결함 밀도를 구할 수 있었다. 또한 같은 특성을 이용하는 Terman의 방법으로 에너지에 따른 계면 결함 밀도를 추출하고, 동일한 에너지 구간에서 평균값을 구하였다. 전압 차이로 구한 평균 계면 결함 밀도를 Terman의 방법으로 구한 평균값과 비교하여, 두 방법의 결과가 거의 비슷한 평균 계면 결함 밀도를 나타낸다는 것을 검증하였다.

Keywords

References

  1. Kyong Taek Lee, Min Sang Park, Chang Yong Kang, Yoon-Ha Jeong, "A Study on Carrier Injection Velocity in sub-100nm SiGe Channel pMOSFETs Using RF C-V Measurement," 2010 IEIE Sumer Conference, pp. 597-598, June 2010.
  2. Muhammad Nawaz, Mikael Ostling, "A Design Evaluation of Strained Si-SiGe on Insulator (SSOI) Based Sub-50 nm nMOSFETs," JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol. 8, No. 3, pp. 136-147, June 2005.
  3. Paek Seung Hyuck, Shim Tae Hun, Moon Joon Seok, Cha Won Jun, and Paek Jae Gun, "Effect of Ge mole fraction and Strained Si Thickness on Electron Mobility of FD n-MOSFET fabricated on Strained Si/Relaxed SiGe/SiO2/Si," Journal of The Institute of Electronics Engineers of Korea, Vol. 41-SD, No. 10, pp. 1-7, October 2004.
  4. Jakub Walczak, Bogdan Majkusiak, "Theoretical Study of Electron Mobility in Double-Gate Field Effect Transistors with Multilayer (strained-)Si/SiGe Channel," JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol. 8, No. 3, pp. 264-275, September 2008. https://doi.org/10.5573/JSTS.2008.8.3.264
  5. Y-J Song, J-W Lim, S-H Kim, H-C Bae, J-Y Kang, K-W Park, K-H Shin, "Effects of Si-cap layer thinning and Ge segregation on the characteristics of Si/SiGe/Si heterostructure pMOSFETs," Solid-State Electronics, 46, pp. 1983-1989, 2002. https://doi.org/10.1016/S0038-1101(02)00139-9
  6. I. Ok, K. Akarvardar, S. Lin, M.Baykan, C. D. Young, P. Y. Hung, M. P. Rodgers, S. Bennett, H. O. Stamper, D. L. Franca, J. Yum, J. P. Nadeau, C. Hobbs, P. Kirsch, P. Majhi, R. Jammy, "Strained SiGe and Si FinFETs for High Performance Logic with SiGe/Si stack on SOI," IEEE IEDM, pp. 776-779, 2010.
  7. T. Ngai, X. Chen, J. Chen, and S. K. Banerjee, "Improving $SiO_2$ / SiGe interface of SiGe p-metal.oxide.silicon field-effect transistors using water vapor annealing," Appl. Phys. Lett., Vol. 80, No. 10, pp. 1773-1775, 11 March 2002. https://doi.org/10.1063/1.1445806
  8. D. Veksler, G. Bersuker, L. Morassi1, J. H. Yum, G. Verzellesi1, Wei-E Wang, P. D. Kirsch, "Extraction of interfacial state density in high-k/III-V gate stacks: problems and solutions," IEEE NMDC, National Cheng Kung Univ., Tainan, Taiwan, October 2013.
  9. Synopsys Inc., Mountain View, CA, Version I-2013. 12, 2013.
  10. Sasa Mileusnic, Milos Zivanov and Predrag Habas, "MOS Transistors Characterization by Split C-V Method," in Proc. of CAS2001, Vol. 2, pp. 503-506, October 2001.
  11. L. M. Terman, "An investigation of surface states at a silicon/silicon oxide interface employing metal-oxide-silicon diodes," Solid-State Electronics, Vol. 5, pp. 285-299, 1962. https://doi.org/10.1016/0038-1101(62)90111-9
  12. D. K. Schroder, Semiconductor material and device characterization, John Wiley & Sons, Inc., pp. 350-352, 2006.