JSTS:Journal of Semiconductor Technology and Science

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Decrease of Parasitic Capacitance for Improvement of RF Performance of Multi-finger MOSFETs in 90-nm CMOS Technology

  • Jang, Seong-Yong (Dept. of Electronics Engineering, Chungnam National University) ;
  • Kwon, Sung-Kyu (Dept. of Electronics Engineering, Chungnam National University) ;
  • Shin, Jong-Kwan (Dept. of Electronics Engineering, Chungnam National University) ;
  • Yu, Jae-Nam (Dept. of Electronics Engineering, Chungnam National University) ;
  • Oh, Sun-Ho (Dept. of Electronics Engineering, Chungnam National University) ;
  • Jeong, Jin-Woong (Dept. of Electronics Engineering, Chungnam National University) ;
  • Song, Hyeong-Sub (Dept. of Electronics Engineering, Chungnam National University) ;
  • Kim, Choul-Young (Dept. of Electronics Engineering, Chungnam National University) ;
  • Lee, Ga-Won (Dept. of Electronics Engineering, Chungnam National University) ;
  • Lee, Hi-Deok (Dept. of Electronics Engineering, Chungnam National University)
  • Received : 2014.08.25
  • Accepted : 2015.03.10
  • Published : 2015.04.30
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Abstract

In this paper, the RF characteristics of multi-finger MOSFETs were improved by decreasing the parasitic capacitance in spite of increased gate resistance in a 90-nm CMOS technology. Two types of device structures were designed to compare the parasitic capacitance in the gate-to-source ($C_{gs}$) and gate-to-drain ($C_{gd}$) configurations. The radio frequency (RF) performance of multi-finger MOSFETs, such as cut-off frequency ($f_T$) and maximum-oscillation frequency ($f_{max}$) improved by approximately 10% by reducing the parasitic capacitance about 8.2% while maintaining the DC performance.

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References

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