DOI QR코드

DOI QR Code

A High-Efficiency CMOS Power Amplifier Using 2:2 Output Transformer for 802.11n WLAN Applications

  • Lee, Ockgoo (Department of Electronic Engineering and PNU-LG Electronics Smart Control Center, Pusan National University) ;
  • Ryu, Hyunsik (Department of Electronic Engineering and PNU-LG Electronics Smart Control Center, Pusan National University) ;
  • Baek, Seungjun (Department of Electronic Engineering and PNU-LG Electronics Smart Control Center, Pusan National University) ;
  • Nam, Ilku (Department of Electronic Engineering and PNU-LG Electronics Smart Control Center, Pusan National University) ;
  • Jeong, Minsu (Raontech) ;
  • Kim, Bo-Eun (Raontech)
  • 투고 : 2014.11.28
  • 심사 : 2015.03.18
  • 발행 : 2015.04.30

초록

A fully integrated high-efficiency linear CMOS power amplifier (PA) is developed for 802.11n WLAN applications using the 65-nm standard CMOS technology. The transformer topology is investigated to obtain a high-efficiency and high-linearity performance. By adopting a 2:2 output transformer, an optimum impedance is provided to the PA core. Besides, a LC harmonic control block is added to reduce the AM-to-AM/AM-to-PM distortions. The CMOS PA produces a saturated power of 26.1 dBm with a peak power-added efficiency (PAE) of 38.2%. The PA is tested using an 802.11n signal, and it satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieves -28-dB EVM at an output power of 18.6 dBm with a PAE of 14.7%.

키워드

참고문헌

  1. D. Guo, "Power amplifier and front end module requirements for IEEE 802.11n applications," High Frequency Electronics, 2011, pp. 38-45.
  2. P. Reynaer and M. S. J. Steyaert, M., "A 2.45-GHz $0.13-{\mu}m$ CMOS PA with parallel amplification," IEEE J. Solid-State Circuits, 2007, vol. 42, no. 3, pp. 551-562. https://doi.org/10.1109/JSSC.2006.891715
  3. C. K. Alexander and M. N. O. Sadiku, Fundamental of electric circuits, 5th ed. MaGRAW-Hill International Edition, 2012.
  4. I. Aoki, S. D. Kee, D. B. Rutledge, and A. Hajimiri, "Distributed activetransformer-a new powercombining and impedance-transformation technique," IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 316-331, Jan. 2002. https://doi.org/10.1109/22.981284
  5. O. El-Charniti, E. Kerherve, and J.-B. Begueret, "Modeling and characterization of on-chip transformers for silicon RFIC," IEEE Trans. Microw. Theory Tech., vol. 55, no. 4, pp. 607-615, Apr. 2007. https://doi.org/10.1109/TMTT.2007.893647
  6. P. Haldi, D. Chowdhury, P. Reynaert, L. Gang, and A. M. Niknejad, "A 5.8 GHz 1 V linear power amplifier using a novel on-chip transformer power combiner in standard 90 nm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1054-1063, May 2008. https://doi.org/10.1109/JSSC.2008.920347
  7. A. B. Afsahi, and L. E. Larson, "A 65nm CMOS 2.4GHz 31.5dBm power amplifier with a distributed LC power-combining network and improved linearization for WLAN applications," ISSCC Dig. Tech. Pprs, San Francisco, CA, USA, February 2010, pp. 452-453.
  8. E. Kaymaksut and P. Reynaert, "Transformer based uneven Doherty power amplifier in 90 nm CMOS for WLAN applications," IEEE J. Solid-State Circuits, 2012, vol. 47, no. 7, pp. 1659-1671. https://doi.org/10.1109/JSSC.2012.2191334
  9. Y. Tan, H. Xu, M. A. El-tanani, and S. Taylor, "A flip-chip-packaged 1.8V 28dBm class-AB power amplifier with shielded concentric transformers in 32nm SoC CMOS," ISSCC Dig. Tech. Pprs, San Francisco, CA, USA, February 2011, pp. 426-427.