JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of Low-Power and Low-Latency 256-Radix Crossbar Switch Using Hyper-X Network Topology

  • Received : 2014.05.12
  • Accepted : 2014.11.17
  • Published : 2015.02.28
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Abstract

This paper presents the design of a low-power, low area 256-radix 16-bit crossbar switch employing a 2D Hyper-X network topology. The Hyper-X crossbar switch realizes the high radix of 256 by hierarchically combining a set of 4-radix sub-switches and applies three modifications to the basic Hyper-X topology in order to mitigate the adverse scaling of power consumption and propagation delay with the increasing radix. For instance, by restricting the directions in which signals can be routed, by restricting the ports to which signals can be connected, and by replacing the column-wise routes with diagonal routes, the fanout of each circuit node can be substantially reduced from 256 to 4~8. The proposed 256-radix, 16-bit crossbar switch is designed in a 65 nm CMOS and occupies the total area of $0.93{\times}1.25mm^2$. The simulated worst-case delay and power dissipation are 641 ps and 13.01 W when operating at a 1.2 V supply and 1 GHz frequency. In comparison with the state-of-the-art designs, the proposed crossbar switch design achieves the best energy-delay efficiency of $2.203cycle/ns{\cdot}fJ{\cdot}{\lambda}2$.

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References

  1. T. Wu, et al., "A 2Gbh 256*256 CMOS Crossbar Switch Fabric Core Design using Pipelined MUX," in Proc. International Symposium on Circuits and Systems (ISCAS), pp. II-568-571, May 2002.
  2. K. Choi, et al., "VLSI Implementation of a 256x256 Crossbar Interconnection Network," in Proc. Parallel Processing Symposium, pp. 289-293, Mar. 1992.
  3. J. Ahn, et al., "Network within a Network Approach to Create a Scalable High-Radix Router Microarchitecture," in Proc. High Performance Computer Architecture (HPCA), pp. 1-12, Feb. 2012.
  4. J. Ahn, et al., "HyperX Topology, Routing, and Packaging of Efficient Large-Scale Networks," in Proc. Conference on High Performance Computing Networking, Storage and Analysis, pp. 14-20, Nov. 2009.
  5. D. Song, et al., "A Low-Power High-Radix Switch Fabric Based on Low-Swing Signaling and Partially-Activated Input Lines," in Proc. VLSI Design, Automation, and Test (VLSI-DAT), pp. 22-24, Apr. 2013.
  6. J. Ryoo, et al., "A 25-FO4, 81-mW Radix-64 Crossbar Switch with Partially-Activated Input and Output Lines," International SoC Conf. (ISOCC), pp. 227-230, Nov. 2012.
  7. G. Passas, et al., "Crossbar NoCs Are Scalable Beyond 100 Nodes," IEEE Trans. Computer-aided Design of Integrated Circuits and Systems, pp. 573-585, Apr. 2012.
  8. G. Passas, et al., "A 128 x 128 x 24Gb/s Crossbar Interconnecting 128 Tiles in A Single Hop and Occupying 6% of Their Area," in Proc. ACM/IEEE International Symposium on Networks-on-Chip, pp. 87-95, May 2010.
  9. F. Moraes, et al., "Estimation of Layout Densities for CMOS Digital Circuits," International Workshop on Power and Timing Modeling Optimization and Simulation (PATMOS), pp. 61-71, Oct. 1998.