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Design of HEVC CABAC Encoder With Parallel Processing of Bypass Bins

우회 빈의 병렬처리가 가능한 HEVC CABAC 부호화기의 설계

  • Kim, Doohwan (School of Electronic Engineering, Soongsil University) ;
  • Moon, Jeonhak (School of Electronic Engineering, Soongsil University) ;
  • Lee, Seongsoo (School of Electronic Engineering, Soongsil University)
  • Received : 2015.12.20
  • Accepted : 2015.12.28
  • Published : 2015.12.31

Abstract

In the HEVC CABAC, the probability model is updated after a bin is encoded and next bin is encoded based on the updated probability model. Conventional CABAC encoders can encode only one bin per cycle, which cannot increase the encoding throughput. The probability model does not need to be updated in the bypass bins. In this paper, a HEVC CABAC encoder is proposed to increase encoding throughput by parallel processing of bypass bins. The designed CABAC encoder can process either a regular bin or maximum 4 bypass bins in a cycle. On the average, it can process 1.15~1.92 bins in a cycle. Synthesized in 0.18 um technology, its gate count, maximum operating speed, and the maximum throughput are 78,698 gates, 136 MHz, and 261 Mbin/s, respectively.

HEVC CABAC에서는 하나의 빈을 부호화한 후 확률 모델을 업데이트하고, 업데이트된 확률 모델로 다음 빈을 부호화한다. 기존 CABAC 부호화기는 매 사이클마다 1개의 빈밖에는 부호화하지 못하여 처리율을 향상시킬 수 없었다. 본 논문에서는 확률 모델의 업데이트가 필요없는 우회 빈을 병렬처리 함으로서 처리율을 높인 HEVC CABAC 부호화기를 제안한다. 설계된 CABAC 부호화기는 매 사이클마다 1개의 정규 빈을 처리하거나 최대 4개의 우회 빈을 처리할 수 있으며, 평균적으로 매 사이클당 1.15~1.92개의 빈을 처리한다. 0.18 um 공정에서 합성한 결과, 게이트 수는 메모리를 포함하여 78,698 게이트, 최대 동작 속도는 136 MHz, 최대 처리율은 261 Mbin/s이다.

Keywords

References

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