Transformer-Less Single-Phase Four-Level Inverter for PV System Applications

Abstract

A new inverter topology for single-phase photovoltaic (PV) systems is proposed in this study. The proposed inverter offers a four-level voltage in its output terminals. This feature results in easier filtering in comparison with other conventional two-level or three-level inverters. In addition, the proposed four-level inverter (PFLI) has a transformer-less topology, which decreases the size, weight, and cost of the entire system and increases the overall efficiency of the system. Although the inverter is transformer-less, it produces a negligible leakage ground current (LGC), which makes this inverter suitable for PV grid-connected applications. The performance of the proposed inverter is compared with that of a four-level neutral point clamped inverter (FLNPCI). Theoretical analysis and computer simulations verify that the PFLI topology is superior to FLNPCI in terms of efficiency and suitability for use in PV transformer-less systems.

I. INTRODUCTION

Among the photovoltaic (PV) systems, grid-connected PV systems and single-phase systems of up to 5 kW play an important role. It is attempted to determine the benefits of these systems. As most of these systems are private, efficiency and reliability should be maximized and size, weight, and cost should be minimized [1], [2]. Depending on the isolation between the PV panels and the grid, the inverter can be either isolated or non-isolated. Isolation is usually achieved using a transformer, which significantly affects the efficiency of the PV system [3]. Isolation occurs in two ways: first, by using a step-up low-frequency transformer in the grid side [Fig. 1(a)]; second, by using a high-frequency transformer in the direct current (DC) side [Fig. 1(b)]. A transformer-less inverter can decrease the weight, size, cost, and installation complexity of the entire PV system (see Fig. 2). A drawback of using transformer-less PV systems is that omitting the transformer induces DC current in the output AC terminal. Semiconductor parameter variations and filter elements may affect the increase in DC current. However, some manufacturing techniques decrease such effects to an acceptable level [4]. One of the important advantages of the transformer-less inverters is an increase in overall system efficiency of up to 2% [5]. Various inverter topologies are proposed in the literature for grid-connected PV systems, such as full-bridge (FB) based or neutral point clamped (NPC)-based [4], [6]-[12].

Fig. 1.Isolation in a grid-connected PV system. (a) Low-frequency transformer in the AC side. (b) High-frequency transformer in the DC side.

Fig. 2.Grid-connected PV system with a transformer-less inverter.

The paper is organized as follows: The proposed topology is studied in Section II. A single-phase four-level NPC inverter (FLNPCI) is considered in Section III. The analysis of losses and LGC are presented in Sections IV and V, respectively. The simulation results are presented in section VII. Section VIII concludes this study.

 

II. PFLI TOPOLOGY

The proposed four-level inverter (PFLI) has ten IGBTs along with freewheeling diodes and three PV sources that have the same voltages. This topology is FB-based and can generate a four-level and symmetrical voltage on its output terminals. The PFLI topology is shown in Fig. 3, where CPV is the parasitic capacitance between the PV panels and ground [13]. This topology is composed of two FB structures with outputs connected to each other. One of them is connected to the middle of the DC bus through two switches (S31 and S32). These two switches enable the middle DC bus voltage to connect to the output directly or inversely without necessarily changing the direction of the output current. Switching states of the PFLI topology for generating a four-level output voltage are listed in Table I. The switches states for each voltage level (++, +, −−, −) are shown in Fig. 4, where the switches states are drawn for positive sign of the current in levels ++ and + and the negative sign of the current in levels − and −−. In voltage level ++ [Fig. 4(a)], switches S11 and S14 are on and the current flows through their IGBTs. When the sign of the current reverses (in non-unity power factors), the current flows through freewheeling diodes of S11 and S14. In voltage level + [Fig. 4(b)], the output current flows through the IGBTs of S21 and S24 and freewheeling diodes of S31 and S32. However, in the case that the power factor is non-unity or in the negative half-cycle of the output current, the current will flow through the freewheeling diodes of S21 and S24 and IGBTs of S31 and S32. In voltage level −− [Fig. 4(c)], switches S12 and S13 are on and the current flows through the IGBTs. In non-unity power factors, where the sign of the current reverses, the current will flow through their corresponding freewheeling diodes. In voltage level – [Fig. 4(d)], the output current flows through the IGBTs of S22 and S23 and the freewheeling diodes of S31 and S32. However, in the case that the power factor is non-unity or in the positive half-cycle of the output current, the current will flow through the freewheeling diodes of S22 and S23 and IGBTs of S31 and S32. To modulate the PFLI switches, a pulse-width modulation (PWM)-based method is used. The modulating and carrier signals of the PWM method are shown in Fig. 5(a). In this figure, CS1, CS2, and CS3 are the carrier signals and MS is the modulating signal. Fig. 5(b) switches gate signals of the PFLI topology in one cycle of fundamental frequency.

Fig. 3.PFLI topology.

TABLE ISWITCHING STATES FOR THE PFLI TOPOLOGY

Fig. 4.Switches states of the PFLI topology in voltage levels. (a) ++. (b) +. (c) −−. (d) −.

Fig. 5.Modulation signals of PFLI switches. (a) Modulating and carrier signals. (b) Switches gate signals.

The desired output voltage from the modulation procedure is shown in Fig. 6. As shown in Fig. 6, the inverter output voltage has four modes. In this figure, modes I and III are derived from modulating CS2 with MS, which results in a switch between + and − levels. The only difference between these modes is the direction of the output current.

Fig. 6.Desired output voltage from PWM.

Mode II is also derived from modulating CS1 with MS, which results in a switch between ++ and + levels. Mode IV is derived from modulating CS3 with MS, which results in a switch between −− and − levels. The voltages of all switches of the PFLI are demonstrated in Table II. As shown in Table II, the maximum voltage that should be tolerated by switches is 3VPV, which is related to S11 to S14. By contrast, switches with the lowest stress are S31 and S32, which have a voltage of 1/4VPV.

TABLE IISWITCH VOLTAGES OF THE PFLI TOPOLOGY

 

III. FLNPCI TOPOLOGY

The NPC topology was introduced by Nabae et al. [14] in 1981. In this topology, switch stress is improved and it can be used in single-phase and three-phase systems [15]. High voltage requirement in the DC bus is the main disadvantage of this topology. If high DC voltage is unavailable, then a boost stage will be required. Thus, the overall efficiency of the system decreases considerably [4]. In this topology, the transient voltage across the inner switches is greater than the outer switches. This finding is due to the fact that the inner switches are not clamped to DC link capacitors same as the outer switches. The inner switches are also directly affected by parasitic components in the system layout [16], [17]. In this section, the topology of single-phase FLNPCI is analyzed.

Unlike the three-phase types of NPC inverters, the single-phase types (in structures with an even number of output voltage levels) encounter the neutral point problem because the neutral wire cannot be connected directly to DC link capacitors.

To solve this problem, bidirectional (four quadrants) switches have to be used to connect the neutral wire to the middle capacitor of the DC link. The FLNPCI topology with asymmetrical DC sources (FLNPCI-ASDC) is shown in Fig. 7. In this topology, the voltage of the middle DC source is half of the other ones. This property allows the FLNPCI-ASDC to provide a symmetrical four-level voltage to its output terminal. By contrast, the FLNPCI topology with symmetrical DC sources (FLNPC-SDC) has identical DC sources in its input. In this case, the magnitude of the levels in the output four-level voltage will not be the same. The FLNPCI-ASDC topology consists of 10 IGBTs with freewheeling diodes and four diodes for clamping. As shown in Fig. 7, the output voltage of PV sources is not identical. If the PV source voltages are equal (FLNPCI-SDC), the low-order current harmonics will be increased, which are difficult to filter, and the levels of the output four-level voltage will not be the same. To resolve this problem, the upper and lower sources should be identical and the middle source should be half the other sources (FLNPCI-ASDC). As a result, the magnitude of the output voltage in each mode will be the same. The FLNPCI-ASDC has five DC sources, whereas the FLNPCI-SDC has three DC sources in its input.

Fig. 7.Single-phase FLNPCI-ASDC topology.

The modulation method for the FLNPCI topology is phase disposition PWM (PDPWM) [18]. Modulating and carrier waveforms for this method are shown in Fig. 5(a). Switching signals generated by the PDPWM method are applied to S1, S2(S8), and S3, and complimentary signals are applied to S4, S5(S7), and S6, respectively. Thus, a four-level voltage will be obtained as output of the inverter. The voltages of all switches in each operational mode are shown in Table III. Based on Table III, the maximum voltage of the switches is 3VPV, which is associated with D12 and D21 . Switches with the lowest stress are S7 and S8, which have the voltage of 1/2VPV.

TABLE IIISWITCH VOLTAGES OF THE FLNPCI-ASDC TOPOLOGY

 

IV. ANALYSIS OF LOSSES

A. Switching Losses

1) Switching Losses of the FLNPCI-ASDC: Given the non-uniform PV resources and switches gate signals, switching losses will differ. The average switching losses of a switch can be approximately expressed as follows [19]:

In (1), tc(off) and tc(on) are the times that the switch is turned off and on completely, respectively, fs is the switching frequency, and Ion and Voff are the current and voltage of the on-state and off-state of the switch, respectively. Assuming that all switches are identical and based on the same switching frequency and current of all switches, the difference factor of switching losses is the difference between off-state voltages (Voff) of the switches; one can write.

According to Table III, in mode I, the switching losses of back to back switches (S7i and S8i, where i = A, B) are related to the 7A (7B) and 8A (8B) IGBTs (diodes). By contrast, in mode III, they are related to the 7B (7A) and 8B (8A) IGBTs (diodes).

Imposing Voff = VPV, we derive the following equation:

In relation to Fig. 5, we observed that

With regard to (4), the operating time of modes I and III (II and IV) are identical. Based on Table III, the switching losses in mode I are the same as those in mode III and those in mode II are the same as those in mode IV. Based on Table I and

the switching losses of IGBTs (PSWI) in t1 and t2-t1 can be represented as follows:

According to the switching losses of diodes (PSWD), we derive the following equation:

With regard to (3) and (4) and Table III, the average switching losses in one cycle of fundamental frequency (see Fig. 5) can be expressed as follows:

Also, it can be deduced,

Thus, based on (7), (8), and (9), we will have:

In (10), PSWIFLNPC -ASDC and PSWDFLNPC -ASDC are the switching losses of the IGBTs and diodes, respectively.

2) Switching Losses of the FLNPC-SDC: In this case, the procedure of obtaining the switching losses equations is similar to the FLNPC-ASDC. The voltages of all switches of the FLNPCI-SDC in each operational mode are shown in Table IV. The switching losses of the IGBTs in t1 and (t2-t1) are expressed as follows:

TABLE IVSWITCH VOLTAGES OF THE FLNPCI-SDC TOPOLOGY

The switching losses of the diodes in t1 and (t2-t1) are:

The switching losses of all semiconductors in one cycle of output fundamental frequency are expressed as follows:

3) Switching Losses of the PFLI: According to Table II, the switching losses of S22 (S21) and S23 (S24) in mode I (mode III) and switching losses of S31 and S32 in modes II and IV are due to their corresponding freewheeling diodes. Based on Table II, the switching losses of IGBTs in t1 and t2-t1 can be expressed as follows:

The switching losses of diodes are:

Based on (8), (14), and (15), the average switching losses of this topology in one cycle of fundamental frequency can be expressed as follows:

where, PSWIPFLI and PSWDPFLI are the switching losses of IGBTs and diodes of the PFLI, respectively.

From (10) and (16), we derive the following equation:

We deduced from (17) that the switching losses of the PFLI topology are lower than those of the FLNPCI-ASDC topology. Based on (13) and (16), one can write,

As shown in (18), the switching losses of the IGBTs of the PFLI are higher than those of the FLNPCI-SDC. However, the switching losses of the diodes of the PFLI are lower than those of the FLNPCI-SDC.

B. Conduction Losses

Conduction losses of a switch can be calculated as follows [19]:

where ton is the on-state time, Ts is the switching period, and Ion and Von are the on-state current and voltage of the switch, respectively. As Ion is identical for all conducting switches and assuming that Von is the same for all conducting switches, the conduction losses of studied topologies can be approximately compared with each other by averaging the conducting switches in one cycle of fundamental frequency.

All conducting switches are shown in Table V for each voltage level of the FLNPCI topology. Based on Table V, the number of conducting switches should be counted in each operational mode. So, we have:

TABLE VCONDUCTING SWITCHES OF THE FLNPCI TOPOLOGY

From (20), Table V, and the fact that modes I and III repeat twice in each cycle of fundamental frequency, it can be written as:

In Table VI, all conducting switches are shown for the PFLI topology in each voltage level. Based on (20), Table V, and the fact that modes I and III repeat twice in each cycle of fundamental frequency, we derive the following equation:

TABLE VICONDUCTING SWITCHES OF THE PFLI TOPOLOGY

Finally, from (21) and (22), we derive the following equation:

Equation (23) shows that the PFLI topology has lower conduction loss in comparison with the FLNPCI topology. We noted that (20) to (23) are valid for the FLNPCI-ASDC and FLNPCI-SDC topologies. However, Ion in (19) is different in these topologies.

 

V. ANALYSIS OF THE LGC

Most PV panels have a metallic frame that should be grounded to satisfy standards. This frame with wide surface of PV panel constructs a parasitic capacitor. As such, one of its electrodes is PV cells and the other is grounded frame. The value of this parasitic capacitance depends on factors such as PV array and grounded frame surface, distance between PV cell and module, dust, and weather conditions. Parasitic capacitance ranges between some nanofarads and some microfarads [20], [21]. When the transformer-less PV system is used to increase efficiency and decrease weight, size, and cost, the isolation between PV panels and grid will be lost. Based on the type of inverter, PV panel, and modulation method, the LGC may exceed the allowed value. This leakage current causes safety problems, increases losses and electromagnetic interference, and injects harmony to the grid [20]-[22]. In other words, the LGC is a common mode current that flows in the ground through a loop. This loop includes PV panel parasitic capacitance, filter elements, inverter, load (grid), and ground. The common mode current and voltage (Vcm and icm) are defined as follows:

Differential mode current and voltage (Vdm and idm) are defined as follows:

In (24) and (25), VAN and VBN are the voltages of A and B terminals related to DC link neutral (N is indicated in Figs. 3 and 7), respectively. In [13] and [23], the common mode model of a PV system is proposed, of which the common mode voltage (CMV) of the system should be constant for non-generating LGC. Equivalent common mode circuit of the studied topologies is shown in Fig. 8, in which LAB = LA║LB. The CMVs of the PFLI and FLNPCI topologies are shown in Tables VII and VIII, respectively. Based on Table VII, we observed that the CMV of the PFLI topology is constant at all times and its LGC is expected to be low. According to Table VIII, the CMV of the FLNPCI-ASDC topology fluctuates at a high frequency and its LGC is expected to be high.

Fig. 8.Common mode model of the studied PV systems.

TABLE VIICOMMON MODE VOLTAGES OF THE PFLI TOPOLOGY

TABLE VIIICOMMON MODE VOLTAGES OF THE FLNPCI-ASDC TOPOLOGY

 

VI. SIMULATION RESULTS

In this section, the PFLI and FLNPCI topologies are compared with each other in terms of output quality, LGC value, and losses. The specifications of the simulated system are shown in Table IX. The PV panel voltages are controlled by means of maximum power point tracker (MPPT). In all simulations, the PV panels are replaced by the ideal DC voltage sources to mitigate the need for MPPT. Based on the VDE 0126-1-1 German standard, the leakage current must have an amplitude less than 300 mA and a root mean square value of up to 30 mA [24]. Fig. 9(a) shows the voltage and current of the PFLI topology. We observed that this topology could produce a four-level voltage in its output terminals. The LGC of this topology is depicted in Fig. 9(b). As expected, the LGC is low, which can evidently satisfy the VDE 0126-1-1 German standard. As such, the PFLI topology can be used in a transformer-less PV system. Figs. 9(c) and 9(d) show the voltage THD (THDv) and current THD (THDi) of the PFLI topology. We observed that the THDi of the PFLI topology is low. The voltage and current of the FLNPCI-ASDC topology are shown in Fig. 10(a). This topology also produces a four-level voltage in its output terminals. Fig. 10(b) shows the LGC. As expected, the LGC is high, which cannot satisfy the standard. Thus, the FLNPCI-ASDC topology cannot be used in transformer-less PV systems. Figs. 10(c) and 10(d) show the THDv and THDi of the FLNPCI-ASDC topology, respectively. The THDi of the FLNPCI-ASDC topology is higher than that of the PFLI topology. The voltage and the current of the FLNPCI-SDC topology are shown in Fig. 11(a). This topology also produces a four-level voltage in its output terminals, but the magnitudes of the operational modes are not identical. In addition, the maximum output voltage of the FLNPCI-SDC topology is lower than that of the PFLI topology.

TABLE IXSIMULATED SYSTEM SPECIFICATIONS

Fig. 9.PFLI waveforms. (a) The inverter voltage and current. (b) The LGC. (c) The THDv. (d) The THDi.

Fig. 10.FLNPCI-ASDC waveforms. (a) The inverter voltage and current. (b) The LGC. (c) The THDv. (d) The THDi.

Fig. 11.FLNPCI-SDC waveforms. (a) The inverter voltage and current. (b) The LGC. (c) The THDv. (d) The THDi.

In Fig. 11(b), the LGC is illustrated. As expected, the LGC is high, which cannot satisfy the standard. Thus, the FLNPCI-SDC topology cannot be used in transformer-less PV systems. Figs. 11(c) and 11(d) show the THDv and THDi of the FLNPCI-SDC topology. The THDi in the FLNPCI-SDC topology is higher than that of other topologies because the magnitudes of the voltage in operational modes are not identical. To simulate the switching and conduction losses of the studied topologies, the PSIM software (from Powersim Inc.) is used. For IGBTs with freewheeling diodes, the characteristics of IKW30N60T (600 V, 30 A) are used. For diodes, the characteristics of CS240650 (600 V, 50 A) are used. The simulation results of the switching and conduction losses are shown in Table X. Based on Table X, we derive the following equations:

Notably, the value of (26) is slightly different from (17). However, (27) and (28) have more significant differences from their theoretical values [(17) and (23)]. This finding is due to the fact that the characteristics of the diodes are different from the characteristics of the freewheeling diodes of the IGBTs in the FLNPCI topology. Comparing (29) to (31) and their corresponding theoretical values [(18) and (23)], a high discrepancy between power losses is observed because the output current of the FLNPCI-SDC topology is lower than that of other topologies (see Figs. 9, 10, and 11).

TABLE XSWITCHING, CONDUCTION, AND TOTAL LOSSES

From Table X, we deduced that the total losses of the PFLI topology is lower than those of other topologies.

 

VII. CONCLUSIONS

In this study, a new inverter topology is proposed for transformer-less PV systems. This topology can generate a four-level voltage in its output terminals, which, in comparison with conventional two-level and three-level topologies, has better quality and easier filtering. Based on the theoretical calculations and simulation results (Table XI), the PFLI topology is superior to the FLNPCI-ASDC topology. The PFLI topology is better than the FLNPCI-SDC topology in terms of the number of semiconductor devices, the maximum output voltage, the conduction and switching losses of diodes, the LGC, and the THDi. The number of PV panels in the PFLI topology is the same as that of the FLNPCI-SDC topology. The maximum switch voltage and switching losses of the IGBTs of the FLNPCI-SDC topology are lower than that of the PFLI topology. Overall, the PFLI topology is superior to the FLNPCI topology because of low construction costs (because of the lower number of switches), low losses, high quality of output waveforms, and suitability for use in transformer-less PV applications (because of low LGC, which decreases the overall losses of the system considerably). In practice, we suggest the use of the previously mentioned semiconductor devices in constructing the PFLI. To control the PFLI, a microcontroller, such as AT91SAM7S256 (ARM-based Flash MCU), is suggested.

TABLE XI*Values in parentheses are based on the simulation results.