References
- A. Shacham, K. Bergman and L. P. Carloni, "On the design of a photonic Network-on-Chip," in Proc. of the First Int. Symp. on Networks-on-Chip, pp. 53-64, Princeton, New Jersey, USA, May 2007.
- H. Gu, K. H. Mo, J. Ku and W. Zhang, "A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip," in Proc. of IEEE Computer Society Annal Symposium 2009, pp. 19-24, Tampa, FL, USA, May 2009.
- Y. Gao, Y. Jin, Z. Chang and W. Hu, "Ultra-low latency reconfigurable Photonic Network on Chip architecture based on application pattern," in Proc. of Optical Fiber Communication 2009, pp. 1-3, San Diego, CA, USA, March 2009.
- C.A. Dit ADI, H. Matsutani, M. Koibuchi, H. Irie, T. Miyoushi and T. Yoshinaga, "An Efficient Path Setup for a Hybrid Photonic Network-on-Chip," in Proc. of International Journal of Networking and Computing 2010, pp. 156-161, Higashi-Hiroshima, Japan ,November 2010.
- Jae Hun Lee, Chang Lin Li, Tae Hee Han, "A Latency Optimization Mapping Algorithm for Hybrid Optical Network-on-Chip," Journal of the Institute of Electronics Engineers of Korea, Vol. 50, no. 7, pp. 131-139, July 2013. https://doi.org/10.5573/ieek.2013.50.7.131
- D. Bertozzi, A. Jalabert, S. Murali, R. Tamhankar, S. Stergiou, L. Benini and G. De. Micheli, "NoC synthesis flow for customized domain specific multiprocessor systems-on-chip," Parallel and Distributed Systems, Vol 16, no. 2, pp. 113-129, February 2005. https://doi.org/10.1109/TPDS.2005.22
- S. Tosun, Y. Ar and S. Ozdemir, "Power-Aware Topology Generation for Application Specific NoC Design," in Proc. of Application of Information and Communication Technologies 2012, pp. 1-6, Tbilisi, Georgia, October 2012.
- K. Goossens, J. Dielissen, O. P. Gangwal, S. G. Pestana, A. Radulescu and E. Rijpkema, "A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification," in Proc. of Design, Automation and Test in Europe 2005, pp. 1182-1187, March 2005.
- H. Gu, Z. Chen, Y. Yang and H. Ding, "RONoC: A Reconfigurable Architecture for Application-Specific Optical Network-on-Chip," IEICE TRANSACTIONS on Information and Systems, Vol. E97-D, no. 1, pp. 142-145, January 2014. https://doi.org/10.1587/transinf.E97.D.142
- Y. Ye, J. Xu, X. Wu, W. Zhang, W. C. Liu and M. Nikdast, "A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip," ACM Journal on Emerging Technologies in Computing Systems, Vol. 8, no. 1, Article No. 5, February 2012.
- R. Min, R. Ji, Q. Chen, L. Zhang and L. Yang, "A Universal Method for Constructing N-Port Nonblocking Optical Router for Photonic Networks-On-Chip," Journal of Lightwave Technology, Vol 30, no. 23, pp. 3736-3741, December 2012. https://doi.org/10.1109/JLT.2012.2227945
- G. Leary, K. Srinivasan, K. Mehta and K. S. Chatha, "Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique," VLSI Systems, Vol 17, no. 5, pp. 674-687, February 2009. https://doi.org/10.1109/TVLSI.2008.2011205
- J. A. Lott, N. N. Ledentsov, V. A. Shchukin, A. Mutig, S. A. Blokhin, A. M. Nadtochiy, G. Fiol and D. Bimberg, "850nm VCSELs for up to 40 Gbit/s Short Reach Data Links," in Proc. of 2010 Conference on Lasers and Electro-Optics (CLEO) and Quantum Electronics and Laser Science Conference (QELS), pp. 1-2, San Jose, CA, USA, May 2010.
- R. B. Dick, D. L. Rhodes and W. Wolf, "TGFF: task graphs for free," in Proc. of the 6th international workshop on Hardware/software codesign , pp. 97-101, Seattle, WA, USA, March 1998.