전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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Pipeline-Aware QC-IRA-LDPC 부호 및 효율적인 복호기 구조

Pipeline-Aware QC-IRA-LDPC Code and Efficient Decoder Architecture

  • 사부흐 (인하대학교 정보통신공학과) ;
  • 이한호 (인하대학교 정보통신공학과)
  • Ajaz, Sabooh (Department of Information and Communication Engineering, Inha University) ;
  • Lee, Hanho (Department of Information and Communication Engineering, Inha University)
  • 투고 : 2014.05.16
  • 심사 : 2014.10.06
  • 발행 : 2014.10.25
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초록

본 논문은 PIPELINE-AWARE QC-IRA-LDPC (PA-QC-IRA-LDPC) 코드 생성 방법과 Rate-1/2 (2016,1008) PA-QC-IRA-LDPC 코드에 대한 효율적인 고속 복호기 구조를 제안한다. 제안한 방법은 비트 오류율 (BER) 성능 저하 없이 파이프라인 기법을 사용하여 임계경로를 나눌 수 있다. 또한 제안한 복호기 구조는 데이터 처리량, 하드웨어 효율 및 에너지 효율을 크게 향상시킬 수 있다. 제안한 복호기 구조는 90-nm CMOS 기술을 사용하여 합성 및 레이아웃이 수행되었으며, 이전에 보고된 복호기 구조들에 비해서 하드웨어 효율성이 53%이상 향상되었고, 훨씬 좋은 에너지 효율성을 보여준다.

This paper presents a method for constructing a pipeline-aware quasi-cyclic irregular repeat accumulate low-density parity-check (PA-QC-IRA-LDPC) codes and efficient rate-1/2 (2016, 1008) PA-QC-IRA-LDPC decoder architecture. A novel pipeline scheduling method is proposed. The proposed methods efficiently reduce the critical path using pipeline without any bit error rate (BER) degradation. The proposed pipeline-aware LDPC decoder provides a significant improvement in terms of throughput, hardware efficiency, and energy efficiency. Synthesis and layout of the proposed architecture is performed using 90-nm CMOS standard cell technology. The proposed architecture shows more than 53% improvement of area efficiency and much better energy efficiency compared to the previously reported architectures.

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참고문헌

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