JSTS:Journal of Semiconductor Technology and Science

  • 제14권4호
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  • Pages.419-426
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  • 2014
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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7.7 Gbps Encoder Design for IEEE 802.11ac QC-LDPC Codes

  • Jung, Yong-Min (School of Electrical & Electronics Engineering, Yonsei University) ;
  • Chung, Chul-Ho (School of Electrical & Electronics Engineering, Yonsei University) ;
  • Jung, Yun-Ho (School of Electronics, Telecommunication and Computer Engineering, Korea Aerospace University) ;
  • Kim, Jae-Seok (School of Electrical & Electronics Engineering, Yonsei University)
  • 투고 : 2013.12.14
  • 심사 : 2014.06.14
  • 발행 : 2014.08.30
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초록

This paper proposes a high-throughput encoding process and encoder architecture for quasi-cyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

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참고문헌

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피인용 문헌

  1. Implementation of IEEE 802.1 ac Down-link MU-MIMO WLAN MAC using Unified Design Methodology vol.16, pp.6, 2016, https://doi.org/10.5573/JSTS.2016.16.6.719