JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

A 45 nm 9-bit 1 GS/s High Precision CMOS Folding A/D Converter with an Odd Number of Folding Blocks

  • Lee, Seongjoo (Department of Semiconductor Science, Dongguk Univ.) ;
  • Lee, Jangwoo (Department of Semiconductor Science, Dongguk Univ.) ;
  • Song, Minkyu (Department of Semiconductor Science, Dongguk Univ.)
  • Received : 2014.01.30
  • Accepted : 2014.05.08
  • Published : 2014.08.30
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, a 9-bit 1GS/s high precision folding A/D converter with a 45 nm CMOS technology is proposed. In order to improve the asymmetrical boundary condition error of a conventional folding ADC, a novel scheme with an odd number of folding blocks is proposed. Further, a new digital encoding technique is described to implement the odd number of folding technique. The proposed ADC employs a digital error correction circuit to minimize device mismatch and external noise. The chip has been fabricated with 1.1V 45nm Samsung CMOS technology. The effective chip area is $2.99mm^2$ and the power dissipation is about 120 mW. The measured result of SNDR is 45.35 dB, when the input frequency is 150 MHz at the sampling frequency of 1 GHz. The measured INL is within +7 LSB/-3 LSB and DNL is within +1.5 LSB/-1 LSB.

Keywords

References

  1. Daeyun Kim and Minkyu Song, "A 65nm 1.2V 7-bit 1GSPS Folding-Interpolation A/D Converter with a Digitally Self-Calibrated Vector Generator", IEICE Transactions on Electronics, Vol. E94-C, No.7, pp.1199-1205, July. 2011. https://doi.org/10.1587/transele.E94.C.1199
  2. Chun-Ying Chen, Michael Q. Le et al., "A Low Power 6-bit Flash ADC With Reference Voltage and Common-Mode Calibration," IEEE Journal of Solid-State Circuits, Vol.44, No. 4, pp. 1041-1046, April. 2009. https://doi.org/10.1109/JSSC.2009.2014701
  3. Xicheng Jiang and Mau-Chung Frank Chang, "A 1-GHz Signal Bandwidth 6-bit CMOS ADC With Power- Efficient Averaging," IEEE Journal of Solid-State Circuits, Vol. 40, No. 2, pp. 532-535, Feb. 2005. https://doi.org/10.1109/JSSC.2004.841033
  4. Robert C. Taft, Chris A. Menkus, et al., "A 1.8-V 1.6-GSample/s 8-b Self-Calibrating Folding ADC With 7.26 ENOB at Nyquist Frequency", IEEE Journal of Solid-State Circuits, Vol. 39, No. 12, pp. 2107-2115, Dec. 2004. https://doi.org/10.1109/JSSC.2004.836242
  5. Klaas Bult and Aaron Buchwald, "An Embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2", IEEE Journal of Solid-State Circuits, Vol. 32, No. 12, pp. 1887-1895 Dec. 1997. https://doi.org/10.1109/4.643647
  6. Alireza Razzaghi, Sai-Wang Tam, et al., "A singlechannel 10b 1GS/s ADC with 1-cycle Latency using Pipelined Cascaded Folding" IEEE Bipolar/BiCMOS circuits and Technology Meeting, pp. 265-268, Oct. 2008.
  7. Joongwon Jun, Daeyun Kim, et al., "A 10-b 500 MS/s CMOS Folding A/D Converter with a Hybrid Calibration and a Novel Digital Error Correction Logic", Journal of Semiconductor Technology and Science, Vol. 12, No.1, pp.1-9, March. 2012. https://doi.org/10.5573/JSTS.2012.12.1.1
  8. Myung-Jun Choe, Band-Sup Song, et al., "An 8-b 100-MSample/s CMOS Pipelined Folding ADC," IEEE Journal of Solid-State Circuits, Vol. 36, No. 2, pp. 184-194, Feb. 2001. https://doi.org/10.1109/4.902759
  9. Zheng-Yu Wang, Hui Pan, et al., "A 600MSPS 8-bit Folding ADC in 0.18um CMOS," IEEE Symposium on VLSI Circuit Dig. Tech. Papaers, pp. 424-427, June. 2004.
  10. Kiyoshi Makigawa, Koichi Ono, et al., "A 7bit 800Msps 120mW folding and Interpolation ADC Using a Mixed-Averaging Schme," IEEE Symposium on VLSI Circuit Dig. Tech. Papaers, pp. 138-139, June. 2006.
  11. Robert C. Taft, Pier Andrea Francese, et al., "A 1.8 V 1.0 GS/s 10b Self-Calibrating Unified- Folding- Interpolating ADC With 9.1 ENOB at Nyquist Frequency," IEEE Journal of Solid-State Circuits, Vol. 44, No. 12, pp. 2107-2115, Dec. 2009.
  12. Mingshuo Wang, Tao Lin, et al., "A 1.2 V 1.0-GS/s 8-bit Voltage-Buffer-Free Folding and interpolating ADC," IEEE International Midwest Symposium on Circuits and Systems, pp. 274-277, Aug. 2012.
  13. Hairong Yu and Mau-Chung Frank Chang, "A 1-V 1.25-GS/S 8-Bit Self-Calibrated Flash ADC in 90-nm Digital CMOS," IEEE Transactions on Circuits and Systems II : Express Briefs, Vol. 55, No.7, pp. 668-672, July. 2008. https://doi.org/10.1109/TCSII.2008.921596
  14. Hyeok-Ki Hong, Wan Kim, Sun-Jae Park, Michael Choi, Ho-Jin Park, and Seung-Tak Ryu, "A 7b 1GS/s 7.2mW Nonbinary 2b/cycle SAR ADC with Register-to-DAC Direct Control," IEEE Custom Integrated Circuits Conference(CICC), pp. 1-4, Sept. 2012.
  15. Ehsan Zhian Tabasy, Ayman Shafik, Shan Huang, Noah Hae-Woong Yang, Sebastian Hoyos, and Samuel Palermo, " A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS," IEEE Journal of Solid-State Circuits, Vol. 48, No. 8, pp. 1885-1897, Aug. 2013. https://doi.org/10.1109/JSSC.2013.2259036
  16. Kostas Doris, Erwin Janssen, Claudio Nani, Athon Zanikopoulos, and Gerard van der Weide, "A 480mW 2.6GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65nm CMOS," IEEE Journal of Solid-State Circuits, Vol. 46, No. 12, pp. 2821-2833, Dec. 2011. https://doi.org/10.1109/JSSC.2011.2164961
  17. Seongjoo Lee, Jangwoo Lee, Mun-Kyo Lee, Sun-Phil Nah, and Minkyu Song, "An 8-b 1GS/s Fractional Folding CMOS Analog-to-Digital Converter with an Arithmetic Digital Encoding Technique,' Journal of Semiconductor Technology and Science (JSTS), Vol. 13,No.5, pp.473-481, Oct. 2013. https://doi.org/10.5573/JSTS.2013.13.5.473