References
- R. R. Tummala, E. J. Rymaszewski and A. G. Klopfenstein, Microelectronics Packaging Handbook, 2nd Ed., Chapman & Hall, London (1997).
- H. S. Choi, W. S. Seo and D. K. Choi, "Prediction of Reliability on Thermoelectric Module through Accelerated Life Test and Physics of Failure", Electron. Mater. Lett., 7(3), 271 (2011). https://doi.org/10.1007/s13391-011-0917-x
- H. J. Chung, S. M. Heo and U. S. Kang, "TSV Technology and Its Application to DRAM", Proc. 2010 IEEE International Solid-State Circuit Conference, San Francisco, 130, IEEE Solid-State Circuits Society (2010).
- S. Kumar, J. Y. Park and J. P. Jung, "Analysis of High Speed Shear Characteristic of Sn-Ag-Cu Solder Joints", Electron. Mater. Lett., 7(4), 365 (2011). https://doi.org/10.1007/s13391-011-0160-5
- Samsung TSV 2013 Diagram 3D Package from http:// www.samsung.com
- Nokia 2013 Packaging Roadmap from http:// www.nokia.com
- P. Dixit, S. Yaofeng, J. Miao, J. H. L. Pang, R. Chatterjee and R. R. Tummala, "Numerical and Experimental Investigation of Thermomechanical Deformation in High Aspect-Ratio Electroplated Through-Silicon Vias", J. Electrochem. Soc., 155(12), H981 (2008). https://doi.org/10.1149/1.2994154
- A. Budiman, H. Shin, B. Kim, S. Hwang, H. Son and M. Suh, "Measurement of Stresses in Cu and Si around Through-Silicon Via by Synchrotron X-Ray Micro Diffraction for 3- Dimensional Integrated Circuits", Microelectron. Reliab., 52(3), 530 (2012). https://doi.org/10.1016/j.microrel.2011.10.016
- K. Lu, S. Ryu, Q. Zhao, K. Hummler, J. Im, R. Huang and P. Ho, "Temperature Dependent Thermal Stress Determination for Through-Silicon-Vias (TSV) by Combining Bending Beam Technique with Finite Element Analysis", Proc. 61th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 1475, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2011).
- M. Amagai and Y. Suzuki, "TSV Stress Testing and Modeling", Proc. 60th ECTC, Las Vegas, 1273, IEEE (CPMT) (2010).
- M. Jung, X. Liu, S. Sitaraman, D. Pan and S. Lim, "Full-Chip Through-Silicon-Via Interfacial Crack Analysis and Optimization for 3D IC", Proc. the International Conference on Computer-Aided Design (ICCAD '11), San Jose, 563, IEEE/ ACM (2011).
- B. Wunderle, R. Mrossko, O. Wittler, E. Kaulfersch, P. Ramm and B. Michel, "Thermo-Mechanical Reliability of 3D-Integrated Microstructures in Stacked Silicon", Proc. 2006 MRS Fall Meeting, Boston, 67, MRS (2007).
- J. Knickerbocker, P. Andry, B. Dang, R. Horton and M. Interrante, "Overview of Candidate Device Technologies for Storage Technology", IBM J. Res. and Develop., 52(5), 449 (2008). https://doi.org/10.1147/rd.524.0449
- "3-D TSV Interconnects", in Equipment & Materials 2008 Report, pp.158, Yole Development, Paris (2008).
- T. Jiang, S. -K. Ryu, Q. Zhao, J. Im, R. Huang and P. S. Ho, "Measurement and Analysis of Thermal Stresses in 3D Integrated Structures Containing Through-Silicon-Vias", Microelectron. Reliab., 53(1), 53 (2013). https://doi.org/10.1016/j.microrel.2012.05.008
- I. H. Jeong, "Electrical Characteristic and Thermal Shock Property of Cu Filled Through Silicon Via for 3-Dimensional Packaging", in Ph.D. Thesis, pp.85, University of Seoul, Seoul (2013).
- X. Liu, Q. Chen, V. Sundaram, R. R. Tummala and S. K. Sitaraman, "Failure Analysis of Through-Silicon Vias in Free- Standing Wafer under Thermal-Shock Test", Microelectron. Reliab., 53(1), 70 (2013). https://doi.org/10.1016/j.microrel.2012.06.140
- K. H. Lu, X. Zhang, S. -K. Ryu, J. Im, R. Huang and P. S. Ho, "Thermo-Mechanical Reliability of 3-D ICs Containing Through Silicon Vias", Proc. 59th ECTC, San Diego, 630, (CPMT) (2009).
- X. Liu, Q. Chen, P. Dixit, R. Chatterjee, R. R. Tummala and S. K. Sitaraman, "Failure Mechanisms and Optimum Design for Electroplated Copper Through-Silicon Vias (TSV)", Proc. 59th ECTC, San Diego, 624, IEEE (CPMT) (2009).
- Z. Zhang, J. Pang, J. Wang, C. Song and D. Yu, "Investigate the Microstructure Changes in Cu Through-Silicon Vias(TSVs) under Thermal Process", Proc. 62th ECTC, San Diego, 1273, IEEE (CPMT) (2012).
- K. H. Lu, S. -K. Ryu, Q. Zhao, X. Zhang, J. Im, R. Huang and P. S. Ho, "Thermal Stress Induced Delamination of Through Silicon Vias in 3-D Interconnects", Proc. 60th ECTC, Las Vegas, 40, IEEE (CPMT) (2010).
- I. H. Jeong, D. H. Jung, K. S. Shin, D. S. Shin and J. P. Jung, "Electrical Characteristics and Thermal Shock Properties of Cu-Filled TSV Prepared by Laser Drilling", Electron. Mater. Lett., 9(4), 389 (2013). https://doi.org/10.1007/s13391-013-0006-4
- D. S. Tezcan, N. Pham, B. Majeed, P. D. Moor, W. Ruythooren and K. Baert, "Sloped Through Wafer Vias for 3D Wafer Level Packaging", Proc. 57th ECTC, Reno, 643, IEEE (CPMT) (2007).
- J. Pak, M. Pathak, S. K. Lim and D. Z. Pan, "Modeling of Electromigration in Through-Slicon-Via Based 3D IC", Proc. 61th ECTC, Lake Buena Vista, 1420, IEEE (CPMT) (2011).
- Z. Chen, Z. Lv, X. Wang, Y. Liu and S. Liu, "Modeling of Electromigration of the Through Silicon Via Interconnects", Proc. 11th International Conference on Electronic Packaging Technology & High Density Packaging (ICEPT-HDP), Xian, 1221, IEEE (2010).
- Y. C. Tan, C. M. Tan, X. W. Zhang, T. C. Chai and D. Q. Yu, "Electromigration Performance of Through Silicon Via (TSV)-a Modeling Approach", Microelectron. Reliab., 50(9), 1336 (2010). https://doi.org/10.1016/j.microrel.2010.07.024
- A. J. Joseph, J. D. Gillis, M. Doherty, P. J. Lindgren, R. A. Previti-Kelly, R. M. Malladi, P. -C. Wang, M. Erturk, H. Ding, E. G. Gebreselasie, M. J. McPartlin and J. Dunn, "Through- Silicon Vias Enable Next-Generation SiGe Power Amplifiers for Wireless Communications", IBM J. Res. Develop., 52(6), 635 (2008). https://doi.org/10.1147/JRD.2008.5388563
- T. Frank, C. Chappaz, P. Leduc, L. Arnaud, S. Moreau, A. Thuaire, R. E. Farhane, F. Lorut and L. Anghel, "Resistance Increase due to Electromigration Induced Depletion under TSV", Proc. IEEE International Reliability Physics Symposium (IRPS '11), Monterey, 341, IEEE (2011).
- S. -H. Seo, J. -S. Hwang, J. -M. Yang, W. -J. Hwang, J. -Y. Song and W. -J. Lee, "Failure Mechanism of Copper Through- Silicon Vias under Biased Thermal Stress", Thin Solid Films., 546, 14 (2013). https://doi.org/10.1016/j.tsf.2013.05.039
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