한국정보통신학회논문지 (Journal of the Korea Institute of Information and Communication Engineering)

  • 제18권7호
  • /
  • Pages.1579-1588
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  • 2014
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  • 2234-4772(pISSN)
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  • 2288-4165(eISSN)
한국정보통신학회 (The Korea Institute of Information and Commucation Engineering)
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1000BASE-T의 4조 PAM-5 신호 상에서 동작하는 비터비 디코더의 구현

Implementation of a Viterbi decoder operated in 4 Dimensional PAM-5 Signal of 1000Base-T

  • Jung, Jae-Woo (Department of Electronic Engineering, Kumoh National Institute of Technology) ;
  • Chung, Hae (Department of Electronic Engineering, Kumoh National Institute of Technology)
  • 투고 : 2014.05.06
  • 심사 : 2014.06.10
  • 발행 : 2014.07.31
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초록

LAN 방식은 국내의 초고속 인터넷 서비스에서 가장 널리 사용되며, UHD TV와 같은 고속의 서비스를 제공하기 위하여 100 메가급에서 1 기가급 이더넷으로 빠르게 전환되고 있다. 1000BASE-T 물리계층은 1 Gbps의 전송속도를 달성하기 위해, 4조의 UTP상에서 각 조당 125 MHz의 PAM-5신호로 데이터를 전송한다. 채널 상에서 발생한 오류를 정정하기 위하여 송신측에서는 컨벌루션 부호와 PAM-5신호를 결합한 TCM을 사용하고, 수신측에서는 비터비 복호기를 사용한다. 본 논문에서는 1000BASE-T의 수신측에서 최소 125 MHz 속도와 최대 2조까지 오류 정정 능력을 제공하는 비터비 디코더를 구현한다. 그리고 구현한 디코더를 논리분석기로 이용해서 동작속도와 오류 정정 능력을 검증한다.

The LAN method is the most widely used in domestic high-speed internet access and rapidly moving to 1 Gbps Ethernet from 100 Mbps one to provide high-speed services such as UHD TV. The 1000BASE-T PHY with 4 pairs UTP transmits a PAM-5 signal at the 125 MHz clock per each pair to achieve 1 Gbps rate. In order to correct errors over the channel, the transmitter uses a TCM which is combined the convolutional encoder and PAM-5, and the receiver uses the Viterbi decoder. In this paper, we implement a Viterbi decoder which can correct two pair errors and operate at the least 125 MHz clock speed. Finally, we will verify the error correction function and the operating speed of the implemented decoder with a logic analyzer.

키워드

참고문헌

  1. Ministry of Science, ICT and Future Planning, Accelerating the Deployment of Giga-Internet. [Internet Press release]. 2013. 5. 3. Available: http://www.msip.go.kr/www/brd/m_211/view.do?seq=89
  2. IEEE Std. 802.3 Section 3, Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) access method and physical layer specifications, IEEE, Piscataway, N.J., 2008.
  3. G. Ungerboeck, "Trellis-Coded Modulation with Redundant Signal Sets," in IEEE communication magazine, vol. 25, no. 2, pp. 5-21, Feb. 1987.
  4. G. Ungerboeck, "Channel coding with multilevel/ phase signals," IEEE transactions on information theory, vol. IT-28, no. 1, pp. 55-67. January 1982.
  5. G. D. Forney, Jr., "The Viterbi Algorithm," in Proceedings of the IEEE, vol. 61, pp. 268-278, March 1973. https://doi.org/10.1109/PROC.1973.9030
  6. J. K. Omura, "On the Viterbi Decoding Algorithm," IEEE transactions on information theory, vol. 15, pp. 177-179, Jan. 1969. https://doi.org/10.1109/TIT.1969.1054239
  7. T. K. Moon, Error Correction Coding, Wiley, pp. 482, 2005.
  8. Rami A. Abdallah, Naresh R. Shanbhag, D. C. Hu, W. Wei, W. C. Lin, H. Lin, "Error-resilient low-power Viterbi decoder architectures," IEEE transactions on signal processing, vol. 57, pp. 4906-4917, 2009. https://doi.org/10.1109/TSP.2009.2026078
  9. W. S. Yu, "Cost-efficient implementation of a parallel processing soft-decision Viterbi decoder with a multi-stage pipelined ACS," M.S. Thesis, Sejong University, Korea, 2010.
  10. T. Y. Kelvin, and Lai, "A high-speed low-power pipelined viterbi decoder: Breaking the ACS-bottleneck," In Green Circuits and Systems(ICGCS) 2010 International Conference on, Shanghai, pp. 334-337, 2010.
  11. B. S. Seo, J. M. Kim, and H. S. Kim, "Parallel structure of Viterbi decoder for high performance of PRML signal," Journal of The Korean Institute of Electrical Engineers, vol. 58, no. 4, pp. 623-626, 2009.
  12. Y. C. Tang, D. C. Hu, W. Wei, W. C. Lin, and H. Lin, "A memory-efficient architecture for low latency Viterbi decoders," In VLSI Design, Automation and Test, 2009. VLSI-DAT'09. International Symposium on. IEEE, Hsinchu, pp. 335-338, 2009.
  13. S. J. Kim, and K. S. Cho, "Design of high-performance Viterbi decoder Circuit by Efficient Management of Path Metric Datav" Journal of IEIE, vol. 47, no. 7, pp. 44-51, 2010.
  14. J. H. Seo, J. C. Seo, and J. K. Kang, "High-Speed Viterbi Decoder Algorithms by Additional Error-Decision Circuitryv" In IEIE 2011 SoC Conference, Korea, pp. 280-284, 2011.
  15. Y. Chu, Y. S. Su, B. S. Lin, P. H. Cheng, and S. J. Chen, "A memoryless Viterbi decoder for LTE systems," The 1st IEEE Global Conference on Consumer Electronics 2012, Tokyo, pp. 643-644, 2012.
  16. S. C. Lee, A high-speed data transmission systems and methods using a cable, KR Patent 10-1193646, to SKT, the Korean Intellectual Property Office. 2012.
  17. H. J. Park et al, 500 Mbps transmission device using 2p line, KR Patent 10-1244009, to KT, the Korean Intellectual Property Office. 2013.
  18. Bernard Sklar, Digital communication: fundamentals and application, Prentice Hall, pp. 314-336, 1988.
  19. H. R. Lee, "A Design of Viterbi Decoder for 1000Base-T," M.S. Thesis, Seoul National University, Korea, 2000.