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Design of the Efficient Multiplier based on Dual Basis

듀얼기저에 기초한 효율적인 곱셈기 설계

  • Park, Chun-Myoung (Department of Computer Engineering, Korea National University of Transportation)
  • 박춘명 (한국교통대학교 컴퓨터공학과)
  • Received : 2014.04.29
  • Accepted : 2014.05.29
  • Published : 2014.06.25

Abstract

This paper proposes the constructing method of effective multiplier using basis transformation. Th proposed multiplier is composed of the standard-dual basis transformation circuit module to change one input into dual basis the operation module to generate from bm to bm+k by the m degree irreducible polynomial, and the polynomial multiplicative module to consist of $m^2$ AND and m(m-1) EX-OR gates. Also, the dual-standard basis transformation circuit module to change the output part to be shown as a dual basis into standard basis is composed. The operation modules to need in each operational part are defined.

본 논문에서는 기저변환을 사용하여 효율적인 곱셈기를 구성하는 방법을 제안하였다. 제안한 곱셈기는 두 입력부분 중 한 입력을 듀얼기저로 변환하는 표준-듀얼 기저 변환회로 모듈과 주어진 m차 기약다항식에 의해 $b_m$부터 $b_{m+k}$를 발생시키는 $b_{m+k}$차 발생연산모듈, $m^2$개의 AND 게이트와 m(m-1)개의 EX-OR 게이트로 구성되는 다항식 승산모듈로 구성된다. 또한, 듀얼기저로 표현되는 출력부분을 표준기저로 변화시켜주는 듀얼-표준 기저 변환회로 모듈로 구성되며, 각 연산부의 구성에 필요한 기본 연산모듈을 정의하였다.

Keywords

References

  1. A. Menezes, I. Blake, S. Gao, R. Mullin, S. Vanstone and T. yaghoobian, Applications of Finite Fields. Kluwer Academic Publisher, 1993.
  2. C.E. Shannon, "A Mathematical Theory of Communication," Bell Syst. Thch. J., 27, pp. 379-423(part I), pp. 623-656 (part II), 2009.
  3. M.T. Lee, Error Correcting Coding Theory, McGraw-Hill, New York, 2010.
  4. R.W. Hamming, "Error Detecting and Error Correcting Codes," Bell Syst. Thch. J., 29, pp. 147-160, 2011.
  5. J. Zhou and O. C. Au,"On the Security of Chaotic Convolutional Coder," IEEE Transaction of Circuit and Systems, Vol.58, No.3, pp.595-606, Mar. 2011. https://doi.org/10.1109/TCSI.2010.2073852
  6. P. A. Scott, S. E. Tarvares and L. E. Peppard, "A Fast Multiplier for GF($2^m$)," IEEE J. Select. Areas Commum., vol. SAC-4, Jan. 2010.
  7. E.D. Mastrovito, "VLSI Design for Multiplication over Finite Fields," LNCS-357, Proc. AAECC-6, pp. 297-309, Rome, July 2012.
  8. J. L. Imana,"Low Latency Polynomial Basis Multiplier,' IEEE Transaction on Circuit and Systems, Vol.58 No.5, pp935-946, May 2011. https://doi.org/10.1109/TCSI.2010.2089553
  9. J. Adikari, A. Barsoum, M.A. Hasan, A.H. Namin, C. Negre,"Improved Area-Time Tradeoffs for Field Multiplication Using Optimal Normal Bases," IEEE Transactions on Computers, Vol.62, No.1, pp.193-199, Jan. 2013. https://doi.org/10.1109/TC.2011.198