DOI QR코드

DOI QR Code

Frequency-ordered 기반 FDR 테스트패턴 압축 알고리즘

FDR Test Compression Algorithm based on Frequency-ordered

  • 문창민 (한양대학교 컴퓨터공학과) ;
  • 김두영 (한양대학교 컴퓨터공학과) ;
  • 박성주 (한양대학교 컴퓨터공학과)
  • Mun, Changmin (Department of Computer Science & Engineering, Hanyang University) ;
  • Kim, Dooyoung (Department of Computer Science & Engineering, Hanyang University) ;
  • Park, Sungju (Department of Computer Science & Engineering, Hanyang University)
  • 투고 : 2013.10.21
  • 심사 : 2014.04.28
  • 발행 : 2014.05.25

초록

최근 반도체 업계에서 주요 관심사로 떠오르고 있는 SOC(System-on-a-chip) 테스트는 비용 및 시간 절감을 위해 여러 종류의 FDR(Frequency-directed run-length) 기술이 제안되었다. 기존의 FDR보다 압축률을 향상시키는 EFDR(Extended-FDR)과 SAFDR(Shifted-Alternate-FDR), VPDFDR(Variable Prefix Dual-FDR)이 있다. 본 논문에서는 제안한 Frequency-ordered 방식은 FDR, EFDR, SAFDR, VPDFDR에 적용시켜 상당한 압축률 개선을 보인다. 본 기술을 사용하면 압축률을 극대화할 수 있고, 결과적으로 전체적인 양산 테스트 비용 및 시간을 크게 절감할 수 있게 한다.

Recently, to reduce test cost by efficiently compressing test patterns for SOCs(System-on-a-chip), different compression techniques have been proposed including the FDR(Frequency-directed run-length) algorithm. FDR is extended to EFDR(Extended-FDR), SAFDR(Shifted-Alternate-FDR) and VPDFDR(Variable Prefix Dual-FDR) to improve the compression ratio. In this paper, a frequency-ordered modification is proposed to further augment the compression ratios of FDR, EFDR, SAFRD and VPDFDR. The compression ratio can be maximized by using frequency-ordered method and consequently the overall manufacturing test cost and time can be reduced significantly.

키워드

참고문헌

  1. Laung-Terng Wang, Xiaqing Wen and Shianling Wu, "Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains" IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, pp. 229-312, Feb 2010.
  2. Xtysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos, "Optimal Selective Huffman Coding for Test-Data Compression," IEEE Trans. on Computer, Vol. 56, no. 8, pp. 1146-1152, August 2007. https://doi.org/10.1109/TC.2007.1057
  3. Shyue-Kung Lu, Hei-Ming Chuang, Guan-Ying Lai, Bi-Ting LaiYa-Chen Huang, "Efficient Test pattern Compression Techniques Based on Complementary Huffman coding" IEEE Circuits and Systems International Conference. ICTD 2009.
  4. Chandra. A, Chakrabarty. K, "System-on-a-chip test-data compression and decompression architectures based on Golomb codes" IEEE Trans, Computer-Aided Design of Integrated Circuits and Systems, Vol, 20, pp. 355-368, Mar 2001. https://doi.org/10.1109/43.913754
  5. Chandra, A, Chakrabarty, K, "Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression" VLSI Test Symposium, IEEE VTS 2001.
  6. El-Maleh, A.H. "Test data compression for system-on-a-chip using extended frequency -directed run-length code", Computers & Digital Techniques, IET, Vol. 2, pp. 155-163, May 2008.
  7. Chandra. A, Chakrabarty. K, "Reduction of SOC test data volume, scan power and testing time using alternating run-length codes", Design Automation Conference, 2002. Proceedings. 39th,
  8. Yang Yu, Zhiming Yang, Xiyuan Peng, "Test Data Compression Based on Variable Prefix Dual-Run-Length Code", IEEE International I2MTC, pp. 2537-2542, May 2012.