JSTS:Journal of Semiconductor Technology and Science

  • 제14권2호
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  • Pages.212-226
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  • 2014
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Design and Implementation of Depth Image Based Real-Time Human Detection

  • 투고 : 2013.08.27
  • 심사 : 2014.02.14
  • 발행 : 2014.04.30
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초록

This paper presents the design and implementation of a pipelined architecture and a method for real-time human detection using depth image from a Time-of-Flight (ToF) camera. In the proposed method, we use Euclidean Distance Transform (EDT) in order to extract human body location, and we then use the 1D, 2D scanning window in order to extract human joint location. The EDT-based human extraction method is robust against noise. In addition, the 1D, 2D scanning window helps extracting human joint locations easily from a distance image. The proposed method is designed using Verilog HDL (Hardware Description Language) as the dedicated hardware architecture based on pipeline architecture. We implement the dedicated hardware architecture on a Xilinx Virtex6 LX750 Field Programmable Gate Arrays (FPGA). The FPGA implementation can run 80 MHz of maximum operating frequency and show over 60fps of processing performance in the QVGA ($320{\times}240$) resolution depth image.

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참고문헌

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