참고문헌
- K. Bult, "Analog Design in Deep Sub-Micron CMOS," in Proc. ESSCIRC, Sep. 2000, pp. 176-184.
- I. Mehr and L. Singer, "A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC," IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 318-325, Mar. 2000. https://doi.org/10.1109/4.826813
- J. Shen and P.R. Kinget, "A 0.5V 8-bit 10-MS/s pipelined ADC in 90nm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 4, April 2008.
- P. C. Yu and H.-S. Lee, "A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC," IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1854-1861, Dec. 1996. https://doi.org/10.1109/4.545805
- J. Crols and M. Steyaert, "Switched-opamp: An approach to realize full CMOS switched-capacitor circuits at very low power supply voltages," IEEE J. Solid-State Circuits, vol. 29, no. 8, pp. 936-942, Aug. 1994. https://doi.org/10.1109/4.297698
-
I. Ahmed and D. A. Johns, "A 50-MS/s (35 mW) to 1-kS/s (15
$\mu$ W) power scalable 10-bit pipelined ADC using rapid power-on opamps and minimal bias current variation," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2446-2455, Dec. 2005. https://doi.org/10.1109/JSSC.2005.856289 - P. J. Hurst and W. J. McIntyre, "Double sampling in switched-capacitor delta-sigma A/D converters," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 1990, pp. 902-905.
- B.-G. Lee and R. M. Tsang, "A 10-bit 50 MS/s pipelined ADC with capacitor-sharing and variablegm opamp," IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 883-890, Mar. 2009. https://doi.org/10.1109/JSSC.2009.2013761
- B. Murmann and B. E. Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040-2050, Dec. 2003. https://doi.org/10.1109/JSSC.2003.819167
- J. K. Fiorenza, T. Sepke, P. Holloway, C. G. Sodini, and H.-S. Lee, "Comparator-based switchedcapacitor circuits for scaled CMOS technologies," IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2658-2668, Dec. 2006. https://doi.org/10.1109/JSSC.2006.884330
- I. Ahmed and D. A. Johns, "A Low-Power Capacitive Charge Pump Based Pipelined ADC," IEEE J. Solid-State Circuits, vol. 45, no. 5, May 2010.
-
J.-H. Eo, S.-H. Kim, M. Kim, and Y.-C. Jang, "A 1.8 V 40-MS/sec 10-bit 0.18-
${\mu}m$ CMOS Pipelined ADC using a Bootstrapped Switch with Constant Resistance," J. lnf. Commun. Converg. Eng. 10(1): 85-90, Mar. 2012. - Lofti, R; Taherzadeh-Sani, M; Yaser Azizi, M; Shoaei, O; " A 1-V MOSFET-only fully-differential dynamic comparator for use in low-voltage pipelined A/D converters," Int. Symp. Signals, Circuits and Systems, July 2003 Page(s):377 - 380 vol.2.
- Wulff, C. (2008). Efficient ADCs for nano-scale CMOS technology. Ph.D. dissertation, Norwegian University of Science and Technology, 2008.
- S. Hashemi, O. Shoaei, "A 0.9V 10-bit 100 MS/s switched-RC pipelined ADC without using a frontend S/H in 90nm CMOS," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), pp.13-16, 18-21 May 2008.