References
- Heiko Schwarz, et al., "Overview of the scalable video coding extension of the H.264/AVC standard," Transaction on circuits and systems for video technology, pp1103-1120, Sep. 2007.
- ISO/IEC 14496-10 International Standard (ITU-T Rec. H.264).
- Yi-Hau Chen., et al., "An H.264/AVC Scalable Extension and High Profile HDTV 1080p Encoder Chip", Symposium on VLSI Circuits Digest of Technical Papers, pp.104-105, 2008.
- Alexis Michael Tourapis, "Direct Mode Coding for Bipredictive Slices in the H.264 Standard", IEEE Transactions on Circuits and Systems for video Technology, Vol. 15, No. 1, Jan. 2005, pp. 119-126. https://doi.org/10.1109/TCSVT.2004.837021
- Kenichi Iwata, et al., "A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits", IEEE JOURNAL OF SOLID-STATE CIRCUITS, pp.59-68, VOL. 45, NO. 1, JANUARY 2010. https://doi.org/10.1109/JSSC.2009.2031797
- Iain E.G. Richardson, H.264 and MPEG-4 video Compression, John Wiley & Sons, Jan 2003, pp. 270.
- M. Horowitz, A. Joch, F.Kossentini, and A. Hallapuro, "H.264/AVC Baseline Profile Decoder Complexity Analysis," IEEE Trans. Circuits Syst. Technol, vol. 13, pp. 704-716, July 2003. https://doi.org/10.1109/TCSVT.2003.814967
- S. M. Park and et al., "A Single-Chip Video/Audio Codec for Low Bit Rate Application", ETRI J., pp. 20-29 vol. 22, no. 1, Mar. 2000.
- S. M. Park and et al., "VLSI Implementation of H.264 Video Decoder for Mobile Multimedia Application," ETRI J., pp. 525-528 vol. 28, no. 4, Aug. 2006. https://doi.org/10.4218/etrij.06.0206.0009
- Sukho Lee, Seongmo Park, and Jongwon Park, "270 MHz Full HD H.264/AVC High Profile Encoder with Shared Multibank Memory-Based Fast Motion Estimation", ETRI J., pp. 784-794 vol. 31, no. 6, Aug. 2009 https://doi.org/10.4218/etrij.09.1209.0007
Cited by
- Software pipelining with CGA and proposed intrinsics on a reconfigurable processor for HEVC decoders pp.1861-8219, 2017, https://doi.org/10.1007/s11554-017-0729-9