Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
권호 표지
DOI QR코드

DOI QR Code

Memory Access for High-Performance Hologram Generation Hardware

고속 홀로그램 생성 하드웨어를 위한 메모리 접근

  • Received : 2013.12.31
  • Accepted : 2014.01.27
  • Published : 2014.02.28
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper we analysis for in out signal by previous study and implement virtual master that generate CGH processor signals. Also, we propose memory address mapping. By constructing the system model of our method and by analyzing the latencies according to the memory access methods in a system including our model and several other models, the low-latency memory access method has been obtained. The proposed method is reduce number of activation in DRAM.

본 논문은 이전 논문들에서 제안한 고속 홀로그램 생성기 구조의 입출력을 분석하여 가상의 마스터(Virtual Master, VM)를 구현하여 홀로그램 생성기의 입출력 신호 패턴을 생성하고, 이를 이용하여 AXI(Advanced eXtensible Interface)기반의 시스템과 연동하여 메모리 접근에 대한 분석하였다. 또한 메모리에 맵핑방법을 통하여 메모리 접근 시 레이턴시를 줄이는 방법을 제안하고 구현한 시스템을 통하여 메모리 접근에 대하여 분석하였다. 제안한 메모리 맵핑 방법을 통하여 분석하였을 때 약 3배 가량 행 활성화(Activation)을 줄여 레이턴시를 줄일 수 있었다.

Keywords

References

  1. T. Motoki, H. Isono, and I. Yuyama, "Present Status of Three-Dimensional Television Research," Proc. IEEE 83(7): 1009-1021(July 1995). https://doi.org/10.1109/5.390119
  2. J. K. Chung and M. H. Tsai, Three-Dimensional Holographic Imaging, John Wiley & Sons, Inc., 2002.
  3. P. Hariharan, Basics of Holography, Cambridge University Press, May 2002.
  4. Mark Lucente, "Interfactive Computation of Holograms Using a Look-up Table", Journal of Electronic Imaging, vol. 2, #1, pp.28-34, Jan. 1993. https://doi.org/10.1117/12.133376
  5. H. Yoshikawa, S. Iwase, and T. Oneda, "Fast Computation of Fresnel Holograms employing Differences", Proceeding of SPIE, vol. 3956, 2000.
  6. T. Shimobaba, T. Ito, "An efficient computational method suitable for hardware of computer-generated hologram with phase computation by addition", Computer Physics Communications, vol. 138, pp. 44-52, 2001. https://doi.org/10.1016/S0010-4655(01)00189-8
  7. N. Masuda, T. Ito, T. Tanaka, A. Shiraki, and T. Sugie, "Computer generated holography using a graphics processing unit," Optics Express, Vol. 14, No. 2, January 2006.
  8. L. Ahrenberg, P. Benzie, M. Magnor, and J. Watson, "Computer generated holography using parallel commodity graphics hardware," Optics Express, Vol. 14, No. 17, August 2006.
  9. Y. Pan, X. Xu, S. Solanki, X. Liang, R. Bin, A. Tanjung, C. Tan, and T.-C. Chong, "Fast CGH computation using S-LUT on GPU", Optics Express, vol. 17, No. 21, pp. 18543-18555, Oct. 2009. https://doi.org/10.1364/OE.17.018543
  10. Y.-Z. Liu, J.-W. Dong, Y.-Y. Pu, B.-C. Chen, H.-X. He, and H.-Z. Wang, "High-speed full analytical holographic computations for true-life scenes", Optics Express, vol. 18, no. 4, pp. 3345-3351, Feb. 2010. https://doi.org/10.1364/OE.18.003345
  11. T. Shimobaba, T. Ito, N, Masuda, Y, Ichihashi, and N. Takada, "Fast calculation of computer-generated-hologram on AMD HD5000 series GPU and OpenCL", Optics Express, vol. 18, no. 10, pp. 9955-9960, May. 2010. https://doi.org/10.1364/OE.18.009955
  12. T. Ito, N. Masuda, K. Yoshimura, A. Shiraki, T. Shimobaba, and T. Sugie, "Special-Purpose computer HORN-5 for a real-time electroholography," Optics Express, Vol. 13, No. 6, March 2005.
  13. Y. Ichihashi, H. Nakayama, T. Ito, N, Masuda, T. Shimobaba, A, Shiraki, and T. Sugie, "HORN-6 specialpurpose clustered computing system for electroholography", Optics Express, vol. 17, no. 16, pp. 13895-13903, Aug, 2009. https://doi.org/10.1364/OE.17.013895
  14. Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, "An architecture of a high-speed digital hologram generator based on FPGA", Journal of Systems Architecture, Vol. 56. pp. 27-37, Dec. 2009.
  15. Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, "A New Parallelizing Algorithm and Cell-based Hardware Architecture for High-speed Generation of Digital Hologram", Journal of Systems Architecture, Vol. 16. pp. 54-63, Jan. 2011. https://doi.org/10.5909/JEB.2011.16.1.054
  16. Y.-H. Seo, Y.-H. Lee, J.-S. Yoo and D.-W. Kim, "Hardware architecture of high-performance digital hologram generator on the basis of a pixel-by-pixel calculation scheme", APPLIED OPTICS, Vol.51 Issue 18, pp. 4003-4012, Jun. 2012. https://doi.org/10.1364/AO.51.004003
  17. Y. S. Chen, S.W. Lo, "Multi-layer bus minimization for SoC", Journal of System and Software, Vol.83, pp.121-132, July 2009.
  18. R. Lu, A. Cao, C. K. Koh, "SAMBA-Bus: A High Performance Bus Architecture for System-on-Chip", IEEE, Vol.15, No.1, pp.69-79, Jan 2007.
  19. K. K. Ryu, V.J. Mooney, "Automated Bus Generation for Multiprocessor SoC Design", IEEE, Vol.23, No.11, Nov 2004.
  20. H. M. Kyung, G. H. Park, J. W. Kwak, T. J. Kim, S. B. Park, "Design and implementation of Performance Analysis Unit(PAU) for AXI-based multi-core System on Chip(SoC)", Microprocessors and Microsystems, Vol.34, pp.102-116, March 2010. https://doi.org/10.1016/j.micpro.2010.03.001
  21. S. Kallakuri, A. Doboli, S. Doboli, "Applying stochastic modeling to bus arbitration for systems-on-chip", Integration, the VLSI journal, Vol.40, pp.183-191, Feb 2006.
  22. J. H. Yoo, S. J. Yoo, K. Y. Choi, "Topology/Floorplan/ Pipeline Co-Design of Cascaded Crossbar Bus", IEEE, Vol.17, No.8, pp.1034-1047, Aug 2009.
  23. R. Wang, Y. Zhan, N. Chou, F. Y. Young, "Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications", IEEE, Vol.30, No.2, pp.167-179, Feb 2011.
  24. S. Pasricha, Y. H. Park, F. J Kurdahi, N. Dutt, "CAPPS: A Framework for Power-Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis", IEEE, Vol.18, No.2, pp.209-221, Feb 2010.
  25. W. Sheng, S. Dong, "Multi-bend bus-driven floorplanning considering fixed-outline constraints", Integration, the VLSI journal, Vol.46, pp.142-152, March 2012.
  26. S. Pasricha, N. D. Dutt, E. Bozorgzadeh, M. B. Romdhane, "FABSYN: Floorplan-Aware Bus Architecture Synthesis", IEEE, Vol.14, No.3, pp.241-253, March 2006.
  27. S. H. Lee, Y. C. Yoon, S. Y. Hwang, "Communicationaware task assignment algorithm for MPSoC using shared memory", Journal of System Architecture, Vol.56, pp.233-241, March 2010. https://doi.org/10.1016/j.sysarc.2010.03.001
  28. Y. C. Lan, H. A. Lin, S. H. Lo, Y. H. Hu, S. J. Chen, "A Bidirectional NoC(BiNoC) Architecture with Dynamic Self-Reconfigurable Channel", IEEE, Vol.30, No.3, March 2011.
  29. C. Wang, W. H. Hu, S. E. Lee, N. Bagherzadeh, "Area and power-efficient innovative congestion-aware Network-on-Chip", Journal of System Architecture, Vol.57, pp.24-38, Oct 2010.
  30. S. Jovanovic, C. Tanougast, C. Bobda, S.Weber, "CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs", Microprocessor and Microsystems, Vol.33, pp.24-36, Aug 2008.
  31. M. Bakhouya, S. Suboh, J. Gaber, T. El-Ghazawi, S. Niar, "Performance evaluation and design tradeoffs of on-chip interconnect architecture", Simulation Modeling Practice and Theory, Vol.19, pp.1496-1505, Nov 2010.
  32. A. Abousamra, A. K. Jones, R. Melhem, "Codesign of NoC and Cache Organization for Reducing Access Latency in Chip Multiprocessors", IEEE. Vol.23, No.6 pp.1038-1046, June 2012.

Cited by

  1. High-Performance Computer-Generated Hologram by Optimized Implementation of Parallel GPGPUs vol.18, pp.6, 2014, https://doi.org/10.3807/josk.2014.18.6.698