참고문헌
- Bang, J.-Y., An, K.-Y., Kim, Y.-D., and Lim, S.-K., A due-date based algorithm for order-lot pegging in a semiconductor wafer fabrication facility. IEEE Trans. Semicond. Manuf, 2008, Vol. 21, p 209-216. https://doi.org/10.1109/TSM.2008.2000261
- Carlyle, M., Knutson, K., and Fowler, J., Bin covering algorithms in the second stage of the lot to order matching problem. J. Oper. Res. Soc, 2001, Vol. 52, p 1232-1243. https://doi.org/10.1057/palgrave.jors.2601222
- Cho, N.W. and Kim, T.S., A Study on Collaboration Strategy Planning of Semiconductor Industry. Journal of the Society of Korea Industrial and Systems Engineering, 2005, Vol. 28, p 139-145.
- Choi, B.K. and Seo, J.C., Capacity-filtering algorithms for finite-capacity planning of a flexible flow Line. Int. J. Prod. Res, 2009, Vol. 47, No. 12, p 3363-3386. https://doi.org/10.1080/00207540701644201
- Fowler, J. and Robinson, J., Measurement and improvement of manufacturing capacities(MIMAC) : Final report. Technical Report 95062861A-TR, SEMATECH, Austin, TX., 1995.
- Fowler, J., Knutson, K., and Carlyle, M., Comparison and evaluation of lot-to-order matching policies for a semiconductor assembly and test facility. Int. J. Prod. Res., 2000, Vol. 38, p 1841-1853. https://doi.org/10.1080/002075400188627
- Kim, J.-G. and Lim, S.-K., Order-lot pegging for minimizing total tardiness in semiconductor wafer fabrication process. J. Oper. Res. Soc., 2012, Vol. 63, p 1258-1270. https://doi.org/10.1057/jors.2011.133
- Knutson, K., Kempf, K., and Fowler, J., Lot-to-order matching for a semiconductor assembly and test facility. IIE Trans, 1999, Vol. 31, p 1103-1111.
- Lim, S.-K., Kim, J.-G., and Kim, H.-J., Simultaneous order-lot pegging and wafer release planning for semiconductor wafer fabrication facilities, Int. J. Prod. Res., 2004, Vol. 52, p 3710-3724.
- Ng, T.S., Sun, Y., and Fowler, J., Semiconductor lot allocation using robust optimization. Eur. J. Oper. Res., 2010, Vol. 205, p 557-570. https://doi.org/10.1016/j.ejor.2010.01.021
- Steiner, G. and Yeomans, J.S., Optimal level schedules in mixed-model, multi-level JIT assembly systems with pegging. Eur. J. Oper. Res., 1996, Vol. 95, p 38-52. https://doi.org/10.1016/0377-2217(95)00254-5
- Wu, T.W., Modular demand and supply pegging mechanism for semiconductor foundry. in Proc. IEEE Int. Symposium on Semicond. Manuf, 2003, p 325-328.
피인용 문헌
- Two-Level Hierarchical Production Planning for a Semiconductor Probing Facility vol.38, pp.4, 2015, https://doi.org/10.11627/jkise.2015.38.4.159
- 반도체 팹에서의 투입 로트 구성을 위한 다차원 동적계획 알고리듬 vol.39, pp.1, 2014, https://doi.org/10.11627/jkise.2016.39.1.073