Journal of Power Electronics

  • 제14권1호
  • /
  • Pages.48-60
  • /
  • 2014
  • /
  • 1598-2092(pISSN)
  • /
  • 2093-4718(eISSN)
전력전자학회 (The Korean Institute of Power Electronics)
권호 표지
DOI QR코드

DOI QR Code

Performance Analysis of a Novel Reduced Switch Cascaded Multilevel Inverter

  • Nagarajan, R. (Dept. of Electrical and Electronic Eng., Raja College of Engineering and Technology) ;
  • Saravanan, M. (Dept. of Electrical and Electronic Eng., Thiagarajar College of Engineering)
  • 투고 : 2012.06.03
  • 발행 : 2014.01.20
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

Multilevel inverters have been widely used for high-voltage and high-power applications. Their performance is greatly superior to that of conventional two-level inverters due to their reduced total harmonic distortion (THD), lower switch ratings, lower electromagnetic interference, and higher dc link voltages. However, they have some disadvantages such as an increased number of components, a complex pulse width modulation control method, and a voltage-balancing problem. In this paper, a novel nine-level reduced switch cascaded multilevel inverter based on a multilevel DC link (MLDCL) inverter topology with reduced switching components is proposed to improve the multilevel inverter performance by compensating the above mentioned disadvantages. This topology requires fewer components when compared to diode clamped, flying capacitor and cascaded inverters and it requires fewer carrier signals and gate drives. Therefore, the overall cost and circuit complexity are greatly reduced. This paper presents modulation methods by a novel reference and multicarrier based PWM schemes for reduced switch cascaded multilevel inverters (RSCMLI). It also compares the performance of the proposed scheme with that of conventional cascaded multilevel inverters (CCMLI). Simulation results from MATLAB/SIMULINK are presented to verify the performance of the nine-level RSCMLI. Finally, a prototype of the nine-level RSCMLI topology is built and tested to show the performance of the inverter through experimental results.

키워드

참고문헌

  1. K.Jang-Hwan, S.-K.Sul, and P.N.Enjeti, "A carrier-based PWM method with optimal switching sequence for a multilevel four-leg voltage source inverter," IEEE Trans. Ind. Appl., Vol. 44, No. 4, pp. 1239-1248,Jul./Aug.2008. https://doi.org/10.1109/TIA.2008.926201
  2. S.Srikanthan and M.K.Mishra, "DC capacitor voltage equalization in neutral clamped inverters for DSTATCOM application," IEEE Trans. Ind. Electron., Vol. 57, No. 8, pp. 2768-2775, Aug. 2010.
  3. L.M.Tolbert,F.Z.Peng, and T.G.Habetler, "Multilevel converters for large electric drives," IEEE Trans. Ind. Appl., Vol. 35, No. 1, pp. 36-44,Jan./Feb. 1999. https://doi.org/10.1109/28.740843
  4. P.Bhagwat, and V.R.Stefanovic, "Generalized structure of a multilevel PWM Inverter," IEEE Trans. Ind. Appln., Vol.1A-19, n.6, pp.1057-1069, Nov/Dec, 1983
  5. R.H.Osman, "A medium-voltage drive utilizing series-cell multilevel topology for outstanding power quality," in Conf. Rec. 34th IEEE IAS Annu. Meeting, 1999, Vol. 4, pp. 2662-2669.
  6. E.Najafi and A.H.M.Yatim, "A novel current mode controller for a static compensator utilizing Goertzel algorithm to mitigate voltage sags," Energy Convers. Manage., Vol. 52, No. 4, pp. 1999-2008, Apr. 2011 https://doi.org/10.1016/j.enconman.2010.11.020
  7. N.Seki and H.Uchino, "Converter configurations and switching frequency for a GTO reactive power compensator," IEEE Trans. Ind. Appl.,Vol. 33, No. 4, pp. 1011-1018, Jul./Aug. 1997. https://doi.org/10.1109/28.605743
  8. G.Shahgholiyan, E.Haghjou, and S.Abazari, "Improving the mitigation of voltage flicker by usage of fuzzy control in a distribution static synchronous compensator (DSTATCOM)," Majlesi J. Elect. Eng., Vol. 3, No. 2,pp. 25-35, Jun. 2009
  9. K.Nakata, K.Nakamura, S.Ito, and K.Jinbo, "A three-level traction inverter with IGBTs for EMU," in Conf. Rec. IEEE IAS Annu. Meeting, 1994, Vol. 1, pp. 667-672
  10. A.Jidin, N.R.N.Idris, A.H.M.Yatim, T.Sutikno, and M.E. Elbuluk, "An optimized switching strategy for quick dynamic torque control in DTC-hysteresis-based induction machines," IEEE Trans. Ind. Electron., Vol. 58, No. 8, pp. 3391-3400, Aug. 2011 https://doi.org/10.1109/TIE.2010.2087299
  11. K.Y.Lau, M.F.M.Yousof, S.N.M.Arshad, M.Anwari, and A.H.M.Yatim,"Performance analysis of hybrid photovoltaic/ diesel energy system under Malaysian conditions," J. Energy, Vol. 35, No. 8, pp. 3245-3255, Aug. 2010. https://doi.org/10.1016/j.energy.2010.04.008
  12. G.M. Martins, J. A. Pomilio, S. Buso, and G. Spiazzi, "Three-phase lowfrequency commutation inverter for renewable energy systems," IEEE Trans. Ind. Electron., Vol. 53, No. 5, pp. 1522-1528, Oct. 2006. https://doi.org/10.1109/TIE.2006.882023
  13. S. Daher, J. Schmid, and F. L. M. Antunes, "Multilevel inverter topologies for stand-alone PV systems," IEEE Trans. Ind. Electron., Vol. 55, No. 7,pp. 2703-2712, Jul. 2008.
  14. E Babaei, "Optimal topologies for cascaded sub-multilevel converters," J. Power Electron., Vol.10, No.3, pp.251-261, May 2010. https://doi.org/10.6113/JPE.2010.10.3.251
  15. E. Beser, B. Arifoglu, S. Camur, and E. K. Beser, "Design and application of a single phase multilevel inverter suitable for using as a voltage harmonic source," J. Power Electron., Vol. 10, No. 2, pp. 138-145, Mar. 2010. https://doi.org/10.6113/JPE.2010.10.2.138
  16. G. Ceglia, V. Guzman, C. Sanchez, F. Ibanez, J. Walter, and M. I. Gimenez, "A new simplified multilevel inverter topology for dc-ac conversion," IEEE Trans. Power Electron., Vol. 21, No. 5, pp. 1311-1319, Sep. 2006.. https://doi.org/10.1109/TPEL.2006.880303
  17. N. A. Rahim, K. Chaniago, and J. Selvaraj, "Single-phase seven-level grid-connected inverter for photovoltaic system," IEEE Trans. Ind. Electron., Vol. 58, No. 6, pp. 2435-2443, Jun. 2011. https://doi.org/10.1109/TIE.2010.2064278
  18. J. Selvaraj and N. A. Rahim, "Multilevel inverter for grid-connected PV system employing digital PI controller," IEEE Trans. Ind. Electron., Vol. 56, No. 1, pp. 149-158, Jan. 2009.
  19. S. G. Song, F. S. Kang, and S.-J. Park, "Cascaded multilevel inverter employing three-phase transformers and single dc input," IEEE Trans. Ind. Electron., Vol. 56, No. 6, pp. 2005-2014, Jun. 2009 https://doi.org/10.1109/TIE.2009.2013846
  20. Fang.Z. Peng, John W.Mckeever, and Donald J.Adams, "A Power line conditioner using Cascade Multilevel Inverters for Distribution systems" IEEE Transactions on Industrial Applications, Vol. 34, n.6, pp 1293-1298, Nov/Dec 1998. al and Power Engineering, Vol. 1, n. 1, Jan 2010, pp 36-40. https://doi.org/10.1109/28.739012
  21. B.P.Mcgrath, D.G.Holmes, "Multicarrier PWM strategies for multilevel inverters," IEEE Trans. IndElectron, vol 49, n.4, pp 858-867,Aug.2002
  22. V.R. Kanetkar and G.K. Dubey, "Series Equivalence/Operation of Current-Controlled Boost-Type SinglePhase Voltage Source Converters for Bidirectional PowerFlow," IEEE.on PE, Vol. 12. No.2 March 1997, pp278-286.
  23. D.G.Holmes and T.A.Lipo, Pulse Width Modulation ForPower Converters (Wiley Inter-science, 2003).
  24. D.G.Holmes and B.P.Mcgrath, "Opportunities for harmonic cancellation with carrier based PWM for two level and multilevel cascaded inverters", in conf.prec IEEE/IAS Annual meeting,1999.
  25. G.Carrara, S.Gardella, M.Marchesoni, R.Salutari,G.Sciutto, "A New Multilevel PWM Method: ATheoretical Analysis," IEEE Trans. Power Electronics,Vol. 7, n.3, July 1992, pp 497-505. https://doi.org/10.1109/63.145137
  26. C.Govindaraju, Dr.K.Baskaran, "Optimized HybridPhase Disposition PWM control method for multilevelinverter" ACEEE Int. Journal on Electrical and PowerEngineering, Vol. 1, n. 1, Jan 2010, pp 36-40.
  27. J.Hamman and F.S.Van Der merwe, "Voltage harmonicsgenerated by voltage fed inverters using PWM naturalsampling" IEEE Trans. Power Electron, vol PE-3,n.3,pp.297-302, Jul.1988.
  28. T.A.Maynard, M.Fadel and N.Aouda, "Modelling ofMultilevel converter," IEEE Trans. Ind.Electron., Vol.44,pp 356-364, Jun.1997. https://doi.org/10.1109/41.585833

피인용 문헌

  1. Reduction of Components in New Family of Diode Clamp Multilevel Inverter Ordeal to Induction Motor vol.16, pp.1, 2016, https://doi.org/10.5573/JSTS.2016.16.1.058
  2. Topologies and Control Strategies of Cascaded Bridgeless Multilevel Rectifiers vol.5, pp.1, 2017, https://doi.org/10.1109/JESTPE.2016.2626788
  3. Voltage Source Inverter Drive Using Error-compensated Pulse Width Modulation vol.16, pp.1, 2016, https://doi.org/10.6113/JPE.2016.16.1.388
  4. An Improved SVPWM Control of Voltage Imbalance in Capacitors of a Single-Phase Multilevel Inverter vol.15, pp.5, 2015, https://doi.org/10.6113/JPE.2015.15.5.1235
  5. A New Symmetric Multilevel Inverter Topology Using Single and Double Source Sub-Multilevel Inverters vol.15, pp.1, 2015, https://doi.org/10.6113/JPE.2015.15.1.96
  6. Calculation of switching loss and current total harmonic distortion of cascaded multilevel grid-connected inverter and Europe efficiency enhancement considering variation of DC source power vol.9, pp.2, 2016, https://doi.org/10.1049/iet-pel.2015.0228
  7. An Improved SPWM Strategy to Reduce Switching in Cascaded Multilevel Inverters vol.16, pp.2, 2016, https://doi.org/10.6113/JPE.2016.16.2.490
  8. Determination Method for Topology Configuration of Hybrid Cascaded H-Bridge Rectifiers vol.16, pp.5, 2016, https://doi.org/10.6113/JPE.2016.16.5.1763
  9. Performance analysis of DVR using “new reduced component” multilevel inverter vol.27, pp.4, 2017, https://doi.org/10.1002/etep.2288
  10. A simple analysis of flying capacitor converter vol.37, pp.3, 2018, https://doi.org/10.1108/COMPEL-07-2017-0282