KIPS Transactions on Computer and Communication Systems (정보처리학회논문지:컴퓨터 및 통신 시스템)

Korea Information Processing Society (한국정보처리학회)
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The Design of Fault Tolerant PSTR Using Virtualization Techniques on the Embedded System

가상화 기술을 이용한 임베디드 시스템상의 고장감내 PSTR 설계

  • 유진호 (백석대학교 정보통신학부) ;
  • 한규종 (건국대학교 인터넷미디어공학과)
  • Received : 2014.09.16
  • Accepted : 2014.10.16
  • Published : 2014.12.31
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Abstract

This paper is a study related to fault tolerant design based on PSTR using virtualization techniques. If the fault tolerant PSTR based on virtualization techniques is implemented the communication performance between primary and shadow will improves and monitoring function is easy to available about activities of primary and shadow. The legacy PSTR model is implemented in its hardware. The primary play a main role and shadow play a switched action when the errors occurrs in the primary. The switched action of shadow make it possible to restart the primary function newly. This paper implements fault tolerant primary-shadow model using virtualization techniques on the embedded environment.

본 논문은 가상화 기술을 이용하여 PSTR에 기반한 고장감내 설계에 관련한 연구이다. 고장감내 PSTR 모델을 가상화 기술에 기반하여 구현하게 되면 프라이머리와 쉐도우 간의 통신성능이 향상되고 각 프라이머리와 쉐도우 내의 동작에 대한 모니터링이 용이하게 된다. 기존의 PSTR 모델은 프라이머리 하드웨어와 쉐도우 하드웨어 구성을 전제로 하여 프라이머리에서 본 임무를 수행하고 쉐도우에서는 프라이머리에서 고장이 발생했을 경우 취해야 할 동작을 준비하게 된다. 쉐도우에서 이러한 동작을 준비하므로 임무에 차질이 없도록 프라이머리는 다시 주 임무를 수행할 수 있게 된다. 본 논문에서는 임베디드 환경에서 고장감내 PSTR 모델을 가상화 기술을 이용하여 구현한다.

Keywords

References

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