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Dual Bias Modulator for Envelope Tracking and Average Power Tracking Modes for CMOS Power Amplifier

  • Ham, Junghyun (Department of Electronic and Electrical Engineering, Sungkyunkwan University) ;
  • Jung, Haeryun (Department of Electronic and Electrical Engineering, Sungkyunkwan University) ;
  • Bae, Jongsuk (Department of Electronic and Electrical Engineering, Sungkyunkwan University) ;
  • Lim, Wonseob (Department of Electronic and Electrical Engineering, Sungkyunkwan University) ;
  • Hwang, Keum Cheol (Department of Electronic and Electrical Engineering, Sungkyunkwan University) ;
  • Lee, Kang-Yoon (Department of Electronic and Electrical Engineering, Sungkyunkwan University) ;
  • Park, Cheon-Seok (Department of Electronic and Electrical Engineering, Sungkyunkwan University) ;
  • Yang, Youngoo (Department of Electronic and Electrical Engineering, Sungkyunkwan University)
  • Received : 2014.08.12
  • Accepted : 2014.10.03
  • Published : 2014.12.30

Abstract

This paper presents a dual-mode bias modulator (BM) for complementary metal oxide semiconductor (CMOS) power amplifiers (PAs). The BM includes a hybrid buck converter and a normal buck converter for an envelope tracking (ET) mode for high output power and for an average power tracking (APT) mode for low output power, respectively. The dual-mode BM and CMOS PA are designed using a $0.18-{\mu}m$ CMOS process for the 1.75 GHz band. For the 16-QAM LTE signal with a peak-to-average power ratio of 7.3 dB and a bandwidth of 5 MHz, the PA with the ET mode exhibited a poweradded efficiency (PAE) of 39.2%, an EVM of 4.8%, a gain of 19.0 dB, and an adjacent channel leakage power ratio of -30 dBc at an average output power of 22 dBm, while the stand-alone PA has a PAE of 8% lower at the same condition. The PA with APT mode has a PAE of 21.3%, which is an improvement of 13.4% from that of the stand-alone PA at an output power of 13 dBm.

Keywords

References

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