ETRI Journal

  • 제35권5호
  • /
  • Pages.808-818
  • /
  • 2013
  • /
  • 1225-6463(pISSN)
  • /
  • 2233-7326(eISSN)
한국전자통신연구원 (Electronics and Telecommunications Research Institute)
권호 표지
DOI QR코드

DOI QR Code

A Flexible Programmable Memory BIST for Embedded Single-Port Memory and Dual-Port Memory

  • Park, Youngkyu (Department of Electrical & Electronic Engineering, Yonsei University) ;
  • Kim, Hong-Sik (Advanced Design Group, R&D, SK Hynix Inc.) ;
  • Choi, Inhyuk (Department of Electrical & Electronic Engineering, Yonsei University) ;
  • Kang, Sungho (Department of Electrical & Electronic Engineering, Yonsei University)
  • 투고 : 2012.10.20
  • 심사 : 2013.03.21
  • 발행 : 2013.10.31
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

Programmable memory built-in self-test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single-port memory and dual-port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility.

키워드

참고문헌

  1. Y. Zorian, E.J. Marinissen, and S. Dey, "Testing Embedded-Core-Based System Chips," IEEE Comput., vol. 32, issue 6, 1999, pp. 52-60.
  2. W.L. Wang, K.J. Lee, and J.F. Wang, "An On-Chip March Pattern Generator for Testing Embedded Memory Cores," IEEE Trans. Very Large Scale Integr. Syst., vol. 9, issue 5, 2001, pp. 730-735. https://doi.org/10.1109/92.953506
  3. A. van de Goor et al., "Low-Cost, Customized and Flexible SRAM MBIST Engine," Proc. Int. Symp. Design Diagnostics Electron. Circuits Syst., 2010, pp. 382-387.
  4. K. Zarrineh, S.J. Upadhyaya, and S. Chakravarty, "A New Framework for Generating Optimal March Tests for Memory Arrays," Proc. Int. Test Conf., Oct. 1998, pp. 73-82.
  5. S. Hamdioui, Z. Al-Ars, and A.J. van de Goor, "Testing Static and Dynamic Faults in Random Access Memories," Proc. VLSI Test Symp., Apr. 2002, pp. 395-400.
  6. A. van de Goor et al., "Generic, Orthogonal and Low-cost March Element Based Memory BIST," Proc. IEEE Int. Test Conf., 2011, pp. 1-10.
  7. C. Cheng et al., "BRAINS: A BIST Compiler for Embedded Memories," Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Syst., Oct. 2000, pp. 299-307.
  8. K. Yamasaki et al., "External Memory BIST for System-in- Package," Proc. Int. Test Conf., Nov. 2005, pp. 1145-1154.
  9. A.W. Hakmi et al., "Programmable Deterministic Built-In Self- Test," Proc. IEEE Int. Test Conf., Oct. 2007, pp. 1-9.
  10. N.Q. Mohd Noor, A. Saparon, and Y. Yusof, "An Overview of Microcode-Based and FSM-Based Programmable Memory Built-in Self-Test (MBIST) Controller for Coupling Fault Detection," Proc. IEEE Symp, Ind. Electron. Appl., Oct. 2009, pp. 469-472.
  11. H.C. Lu and J.F. Li, "A Programmable Online/Off-line Built-in Self-Test Scheme for RAMs with ECC," Proc. Int. Symp. Circuits Syst., May 2009, pp. 1997-2000.
  12. X. Du et al., "Full-Speed Field-Programmable Memory BIST Architecture," Proc. IEEE Int. Test Conf., Nov. 2005, pp. 1165-1173.
  13. X. Du et al., "A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops," Proc. IEEE Asian Test Symp., Nov. 2006, pp. 287-292.
  14. Y. Park et al., "An Effective Programmable Memory BIST for Embedded Memory," IEICE Trans. Inf. Syst., vol. E92-D, no. 12, Dec. 2009, pp. 2508-2511. https://doi.org/10.1587/transinf.E92.D.2508
  15. A. Benso et al., "A Programmable BIST Architecture for Clusters of Multiple-port SRAMs," Proc. IEEE Int. Test Conf., Oct. 2000, pp. 557-566.
  16. M. Karunaratne and B. Oomman, "Optimized BIST for Embedded Dual-Port RAMs," Proc. IEEE Midwest Symp. Circuits Syst., Aug. 2010, pp. 125-128.
  17. S. Hamdioui and A.J. van de Goor, "Efficient Tests for Realistic Faults in Dual-Port SRAMs," IEEE Trans. Comput., vol. 51, issue 5, 2002, pp. 460-473. https://doi.org/10.1109/TC.2002.1004586
  18. Y. Park et al., "An Effective Test and Diagnosis Algorithm for Dual-Port Memories," ETRI J., vol. 30, no. 4, Aug. 2008, pp. 555-564. https://doi.org/10.4218/etrij.08.0107.0348
  19. Samsung $0.13{\mu}m$ Generic Process Compiled Memory (STD150E), Data Book of Samsung Electronics, May 2005.
  20. S. Hamdioui, A.J. van de Goor, and M. Rodgers, "March SS: A Test for All Static Simple RAM Faults," Proc. IEEE Int. Workshop Memory Technol., Design, Testing, July 2002, pp. 95-100.

피인용 문헌

  1. Fully Programmable Memory BIST for Commodity DRAMs vol.37, pp.4, 2013, https://doi.org/10.4218/etrij.15.0115.0040
  2. A Programmable IEEE 1500-Compliant Wrapper for Testing of Word-Oriented Memory Cores vol.27, pp.9, 2013, https://doi.org/10.1142/s0218126618501347