References
- Floyd M. Gardner, "Charge-Pump Phase-Lock Loop", IEEE J. Tran, on Communications, vol. COM-28, no. 11, pp. 1849-1858, Nov. 1980.
- S. J. Yun, H. D. Lee, K. D. Kim and J. K. Kwoni, "Differentially-tuned low-spur PLL using 65nm CMOS process," Electronics Letters, vol. 47, no. 6, pp. 369-371, Mar. 2011. https://doi.org/10.1049/el.2011.0166
- M. M. Elsayed, M. Abdul-Latif, E. Sanchez-Sinencio "A spur-frequency-boosting PLL with a 074dBc reference-spur suppression in 90nm digital CMOS" IEEE J. Solid-State Circuits, vol. 48, no. 9, pp. 2104-2117, Sept. 2013. https://doi.org/10.1109/JSSC.2013.2266865
- T. C. Lee and B. Razavi, "A stabilization technique for phase-locked frequency synthesizers," IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 888-894, Jun. 2003. https://doi.org/10.1109/JSSC.2003.811879
- A Maxim et al., "A low-jitter 125-1250-MHz processindependent and ripple-poleless 0.18-um CMOS PLL based on a sample-reset loop filter," IEEE J. Solid-State Circuit, vol. 36, no. 11, pp. 1673-1683, Nov. 2001. https://doi.org/10.1109/4.962287
- J. G Maneatis et al., "Self-biased, High-bandwidth, low-jitter 1-to-4096 multiplier clock-generator PLL," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1795-1803, Nov. 2003. https://doi.org/10.1109/JSSC.2003.818298
- Jaeha Kim, Jeong-Kyoum Kim, Bong-Joon Lee, Namhoon Kim, Deog-Kyoon Jeong and Wonchan Kim, "A20-GHz Phase-Locked Loop for 40-Gb/s Serializing Transmitterin 0.13-um CMOS", IEEE Journal of Solid-State Circuits, vol. 41, no. 4, April 2006.
- Youn-Gui Song, Young-Shig Choi, "A Fast Locking Phase Locked Loop with Multiple Charge Pumps", IEEK Journal of Electronics Engineers of Korea-SD, vol. 46, no. 2 pp. 71-77, February 2009.