DOI QR코드

DOI QR Code

A Spread Spectrum Clock Generator for DisplayPort 1.2 with a Hershey-Kiss Modulation Profile

  • Received : 2012.12.26
  • Accepted : 2013.04.25
  • Published : 2013.08.31

Abstract

This paper describes a spread spectrum clock generator (SSCG) circuit for DisplayPort 1.2 standard. A Hershey-Kiss modulation profile is generated by dual sigma-delta modulators. The structure generates various modulation slopes to shape a non-linear modulation profile. The proposed SSCG for DisplayPort 1.2 generates clock signals with 5000 ppm down spreading with a Hershey-Kiss modulation profile at three different clock frequencies, 540 MHz, 270 MHz and 162 MHz. The measured peak power reduction is about 15.6 dB at 540 MHz with the chip fabricated using a $0.13{\mu}m$ CMOS technology.

Keywords

References

  1. K. B. Hardin, J. T. Fessler, and D. R. Bush, "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions," in Proc. IEEE International Symposium on Electromagnetic Compatibility, pp.227-231, Aug., 1994.
  2. K. Hardin, R. A. Oglesbee, and F. Fisher, "Investigation Into the Interference Potential of Spread-Spectrum Clock Generation to Broadband Digital Communications," IEEE Transactions on Electromagnetic Compatibility, Vol.45, No.1, pp.10-21, Feb., 2003. https://doi.org/10.1109/TEMC.2002.808074
  3. D. D. Caro, C. A Romani, A. G. Maria, and C. Parrella, "A 1.27GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65nm CMOS," IEEE J. Solid-State Circuits, Vol.45, No.5, pp.1048-1060, May 2010. https://doi.org/10.1109/JSSC.2010.2043461
  4. M. Song, S. Ahn, I. Jung, Y. Kim, and C. Kim, "1.5 GHz Spread Spectrum Clock Generator with a 5000ppm Piecewise Linear Modulation," in Proc. IEEE CICC, pp. 455-458, Sep., 2008.
  5. S. Hwang, M. Song, Y. Kwak, I. Jung and C. Kim, "A 0.076mm2 3.5GHz Spread-Spectrum Clock Generator with Memoryless Newton-Raphson Modulation Profile in 0.13${\mu}m$ CMOS" in Proc. IEEE ISSCC Dig. of Tech papers, Feb., 2011.
  6. H. R. Lee, O. Kim, G. Ahn, and D. K. Jeong, "A low-jitter 5000ppm spread spectrum clock generator for multi-channel SATA transceiver in 0.18${\mu}m$ CMOS," in Proc. IEEE ISSCC Dig. of Tech Papers, pp.162-163, Feb., 2005.
  7. W. T. Chen, J. C. Hsu, H. W. Lune and C. C. Su, "A Spread Spectrum Clock Generator for SATAII," IEEE International Symposium on Circuits and Systems, pp.2643-2646, May 2005.
  8. M. Kokubo, T. Kawamoto, T. Oshima, T. Noto, M. Suzuki, S. Suzuki, T. Hayasaka, T. Takahashi and J. Kasai, "Spread-Spectrum Clock Generator for Serial ATA using Fractional PLL Controlled by $\Delta{\Sigma}$ Modulator with Level Shifter," in Proc. IEEE ISSCC Dig. of Tech Papers, pp.160-161, Feb., 2005.
  9. D. S. Kim and D. K. Jeong, "A Spread Spectrum Clock Generation PLL with Dual-tone Modulation Profile" Symposium on VLSI Circuits Dig. of Tech Papers, pp.96-99, June 2005.
  10. J. W. Lee, H. J. Kim, C. Yoo, "Spread Spectrum Clock Generation for Reduced Electro-Magnetic Interference in Consumer Electronics Devices", IEEE Transactions on Consumer Electronics, Vol. 56, No.2, pp.844-847, May 2010. https://doi.org/10.1109/TCE.2010.5506010
  11. H. Park and J. Kang, "SSCG with Hershey-Kiss modulation profile using Dual Sigma-Delta modulators", IEICE Express, Vol.7, No.18, pp.1349-1353, Sep., 2010. https://doi.org/10.1587/elex.7.1349
  12. VESA, VESA DisplayPort Standard, version 1, Revision 2, Jan. 2010.
  13. K. J. Wang, A. Swaminathan, and I. Galton, "Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL," IEEE J. Solid-State Circuits, Vol.43, No.12, pp.2787-2797, Dec., 2008. https://doi.org/10.1109/JSSC.2008.2005716
  14. J. G. Maneatis, "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE J. Solid-State Circuits, Vol.31, No.11, pp.1723-1732, Nov., 1996. https://doi.org/10.1109/JSSC.1996.542317
  15. I. A. Young, "A PLL Clock Generator With 5 to 110 MHz of Lock Range for Microprocessors", IEEE J. Solid-State Circuits, Vol. 27, No. 11, pp. 1599-1607, Nov., 1992. https://doi.org/10.1109/4.165341
  16. M. Kokubo, T. Kawamoto, T. Oshima, T. Noto, M. Suzuki, S. Suzuki, T. Hayasaka, T. Takahashi, and J. Kasai, "Spread-Spectrum Clock Generator for Serial ATA with Multi-Bit Sigma-Delta Modulator-Controlled Fractional PLL," IEICE Trans. Electron., Vol. E89-C, No.11, pp.1682- 1688, Nov., 2006. https://doi.org/10.1093/ietele/e89-c.11.1682
  17. M. Aoyama et al., "3 Gbps, 5000 ppm Spread Spectrum SerDes PHY with Frequency Tracking Phase Interpolator for Serial ATA," Symposium on VLSI Circuits Dig. of Tech Papers, pp.107-110, June 2003.
  18. D. S. Shen, and S. I. Liu, "A Low-Jitter Spread Spectrum Clock Generator using FDMP," IEEE Trans. Circuits and Systems II, Vol.54, No.11, pp.979-983, Nov., 2007. https://doi.org/10.1109/TCSII.2008.919993
  19. F. Pareschi, G. Setti, and R. Rovatti, "A 3-GHz Serial ATA Spread-Spectrum Clock Generator Employing a Chaotic PAM Modulation," IEEE Trans. Circuits and Systems I, Vol.57, No.10, pp.2577-2587, Oct., 2010. https://doi.org/10.1109/TCSI.2010.2048771