DOI QR코드

DOI QR Code

An Efficient Interpolation Hardware Architecture for HEVC Inter-Prediction Decoding

  • Jin, Xianzhe (Graduate School of Information and Communication, Hanbat National University) ;
  • Ryoo, Kwangki (Graduate School of Information and Communication, Hanbat National University)
  • 투고 : 2012.12.14
  • 심사 : 2013.03.18
  • 발행 : 2013.06.30

초록

This paper proposes an efficient hardware architecture for high efficiency video coding (HEVC), which is the next generation video compression standard. It adopts several new coding techniques to reduce the bit rate by about 50% compared with the previous one. Unlike the previous H.264/AVC 6-tap interpolation filter, in HEVC, a one-dimensional seven-tap and eight-tap filter is adopted for luma interpolation, but it also increases the complexity and gate area in hardware implementation. In this paper, we propose a parallel architecture to boost the interpolation performance, achieving a luma $4{\times}4$ block interpolation in 2-4 cycles. The proposed architecture contains shared operations reducing the gate count increased due to the parallel architecture. This makes the area efficiency better than the previous design, in the best case, with the performance improved by about 75.15%. It is synthesized with the MagnaChip $0.18{\mu}m$ library and can reach the maximum frequency of 200 MHz.

키워드

참고문헌

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  7. M. T. Pourazad, C. Doutre, M. Azimi, and P. Nasiopoulos, "HEVC: the new gold standard for video compression: How Does HEVC Compare with H.264/AVC?," IEEE Consumer Electronics Magazine, vol. 1, no. 3, pp. 36-46, 2012.
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피인용 문헌

  1. Design of Sub-pixel Interpolation Circuit for Real-time Multi-decoder Supporting 4K-UHD Video Images vol.19, pp.1, 2015, https://doi.org/10.7471/ikeee.2015.19.1.001
  2. Hardware-software implementation of HEVC decoder on Zynq vol.79, pp.11, 2013, https://doi.org/10.1007/s11042-019-08548-3