DOI QR코드

DOI QR Code

The Short Channel Effect Immunity of Silicon Nanowire SONOS Flash Memory Using TCAD Simulation

  • Yang, Seung-Dong (Department of Electronics Engineering, Chungnam National University) ;
  • Oh, Jae-Sub (Department of Electronics Engineering, Chungnam National University) ;
  • Yun, Ho-Jin (Department of Electronics Engineering, Chungnam National University) ;
  • Jeong, Kwang-Seok (Department of Electronics Engineering, Chungnam National University) ;
  • Kim, Yu-Mi (Department of Electronics Engineering, Chungnam National University) ;
  • Lee, Sang Youl (Department of Electronics Engineering, Chungnam National University) ;
  • Lee, Hi-Deok (Department of Electronics Engineering, Chungnam National University) ;
  • Lee, Ga-Won (Department of Electronics Engineering, Chungnam National University)
  • Received : 2013.01.22
  • Accepted : 2013.03.21
  • Published : 2013.06.25

Abstract

Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage ($V_T$) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

Keywords

References

  1. Y. Shin, VLSI Circuits, Symposium on VLSI Symp. Tech. Dig., pp.156-159 (2005) DOI: 10.1109/VLSIC.2005.1469355.
  2. Y. Yang, M. H. White, Solid-State Elec., Vol. 44, pp. 949-958 (2000) [DOI: http://dx.doi.org/10.1016/S0038-1101(00)00012-5].
  3. Tzu-Hsuan Hsu, Hang-Ting Lue, and Chih-Yuan Lu, VLSI Circuits, Symposium on VLSI Symp. Tech. Dig., pp. 154-155 (2009) [DOI: http://dx.doi.org/10.1109/VTSA.2009.5159336].
  4. Y. Cui, Z. Zhong, D. Wang, W. Wang, and C. M. Lieber, Nano Lett., vol. 3, no. 2, pp. 149.152, (2003) [DOI: http://dx.doi.org/10.1021/nl025875l].
  5. F.-L. Yang, D. H. Lee, H. Y. Chen, and C. Hu, VLSI Symp. Tech. Dig., 2004, pp. 196.197 [DOI: http://dx.doi.org/10.1109/VLSIT.2004.1345476].
  6. S. D. Suk, S.-Y. Lee, S.-M. Kim, and B.-I. Ryu, IEDM Tech. Dig., 2005, pp. 717.720 [DOI: http://dx.doi.org/10.1109/IEDM.2005.1609453].
  7. K. H. Yeo, S. D. Suk, M. Li, and B.-I. Ryu, IEDM Tech. Dig., 2006, pp. 539.542 [DOI: http://dx.doi.org/10.1109/IEDM.2006.346838].
  8. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, (1998).
  9. K. Asano, Y.-K. Choi, T.-J. King, and C. Hu, IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 1004.1006, May (2001) [DOI: http://dx.doi.org/10.1109/16.918251].
  10. R. M. Y. Ng, T. Wang, F. Liu, X. Zuo, J. He, and M. Chan, IEEE Electron Device Lett., vol. 30, no. 5, pp. 520.522, May (2009) [DOI: http://dx.doi.org/10.1109/LED.2009.2014975].
  11. S. Bangsaruntip, G. M. Cohen, A. Majumdar, and J. W. Sleight, IEEE Electron Device Lett., vol. 31, no. 9, pp. 903-905, Sep (2010) [DOI: http://dx.doi.org/10.1109/LED.2010.2052231].

Cited by

  1. Investigation of Physically Unclonable Functions Using Flash Memory for Integrated Circuit Authentication vol.14, pp.2, 2015, https://doi.org/10.1109/TNANO.2015.2397956
  2. Silicon-Based BioFETs with 3-D Nanostructure: Easy integration, precise control of nanostructure, and a low device-to-device variation vol.10, pp.3, 2016, https://doi.org/10.1109/MNANO.2016.2573478