JSTS:Journal of Semiconductor Technology and Science

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Device and Circuit Level Performance Comparison of Tunnel FET Architectures and Impact of Heterogeneous Gate Dielectric

  • Narang, Rakhi (Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi) ;
  • Saxena, Manoj (Department of Electronics, Deen Dayal Upadhyaya, College, University of Delhi) ;
  • Gupta, R.S. (Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology) ;
  • Gupta, Mridula (Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi)
  • Received : 2012.09.29
  • Accepted : 2012.11.07
  • Published : 2013.06.30
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Abstract

This work presents a comparative study of four Double Gate tunnel FET (DG-TFET) architectures: conventional p-i-n DG-TFET, p-n-p-n DG-TFET, a gate dielectric engineered Heterogate (HG) p-i-n DG-TFET and a new device architecture with the merits of both Hetero Gate and p-n-p-n, i.e. HG p-n-p-n DG-TFET. It has been shown that, the problem of high gate capacitance along with low ON current for a p-i-n TFET, which severely hampers the circuit performance of TFET can be overcome by using a p-n-p-n TFET with a dielectric engineered Hetero-gate architecture (i.e. HG p-n-p-n). P-n-p-n architecture improves the ON current and the heterogeneous dielectric helps in reducing the gate capacitance and suppressing the ambipolar behavior. Moreover, the HG architecture does not degrade the output characteristics, unlike the gate drain underlap architecture, and effectively reduces the gate capacitance.

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References

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