한국항행학회논문지 (Journal of Advanced Navigation Technology)

  • 제17권1호
  • /
  • Pages.69-79
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  • 2013
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  • 1226-9026(pISSN)
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  • 2288-842X(eISSN)
한국항행학회 (The Korean Navigation Institute)
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병행설계를 이용한 H.264/AVC의 DCT 및 CAVLC 하드웨어 구현

Hardware Implementation of DCT and CAVLC for H.264/AVC based on Co-design

  • 왕덕상 (엘지전자 카사업부) ;
  • 서석용 (광운대학교 전자통신공학과) ;
  • 고형화 (광운대학교 전자통신공학과)
  • Wang, Duck-Sang (LG Electronics. co. Ltd.) ;
  • Seo, Seok-Yong (Dept. of Electronics and Communication Eng., Kwang-Woon University) ;
  • Ko, Hyung-Hwa (Dept. of Electronics and Communication Eng., Kwang-Woon University)
  • 투고 : 2013.01.22
  • 심사 : 2013.02.28
  • 발행 : 2013.02.28
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초록

본 논문에서는 H.264/AVC의 부호기를 제작하기 위하여 DCT(Discrete Cosine Transform) 부호화와 엔트로피 부호화인 CAVLC(Context-Adaptive Variable Length Coding)를 하드웨어 IP로 설계하고 나머지 부분은 소프트웨어로 설계하는 병행설계(Co-Design)방법을 이용하였다. DCT 및 Hadamard 변환의 처리속도를 개선하기 위하여 Shift table을 제안하여 기존의 방식보다 16(%)정도 빠른 연산이 가능했다. 설계된 IP들은 Xilinx ML410보드의 Virtex-4 FX60 FPGA에 다운로드하여 MicroBlaze CPU를 이용하여 H.264/AVC의 참조 소프트웨어인 JM13.2와 연동이 가능하도록 설계하였다. 검증을 위해 각 IP에 대한 기능 시뮬레이션을 ModelSim을 이용하여 수행하였다. 마지막으로 실제 FPGA에 포팅하여 정상 동작여부를 확인하였다. 실험 결과 MicroBlaze를 이용한 S/W 연산시와 비교하여 H/W를 이용할 경우 DCT는 약 16배, CAVLC는 약 10배 빠른 처리 속도를 나타내었다. 본 연구는 H.264시스템의 H/W와 S/W의 병행설계에 관한 것이지만, 개발에 사용한 방법은 다른 임베디드 시스템 개발에도 유용하게 사용할 수 있다.

In this paper, DCT(Discrete Cosine Transform) and CAVLC(Context Adaptive Variable Length Coding) are co-designed as hardware IP with software operation of the other modules in H.264/AVC codec. In order to increase the operation speed, a new method using SHIFT table is proposed. As a result, enhancement of about 16(%) in the operation speed is obtained. Designed Hardware IPs are downloaded into Virtex-4 FX60 FPGA in the ML-410 development board and H.264/AVC encoding is performed with Microblaze CPU implemented in FPGA. Software modules are developed from JM13.2 to make C code. In order to verify the designed Hardware IPs, Modelsim program is used for functional simulation. As a result that all Hardware IPs and software modules are downloaded into the FPGA, improvement of processing speed about multiples of 16 in case of DCT hardware IP and multiples of 10 in case of CAVLC compared with software-only processing. Although this paper deals with co-design of H/W and S/W for H.264, it can be utilized for the other embedded system design.

키워드

참고문헌

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