Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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A 10-bit 10-MS/s 0.18-㎛ CMOS Asynchronous SAR ADC with split-capacitor based differential DAC

분할-커패시터 기반의 차동 디지털-아날로그 변환기를 가진 10-bit 10-MS/s 0.18-㎛ CMOS 비동기 축차근사형 아날로그-디지털 변환기

  • 정연호 (금오공과대학교 전자공학과) ;
  • 장영찬 (금오공과대학교 전자공학부)
  • Received : 2012.12.13
  • Accepted : 2012.12.26
  • Published : 2013.02.28
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Abstract

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of $140{\times}420{\mu}m^2$ is fabricated using a 0.18-${\mu}m$ CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.

본 논문은 분할-커패시터 기반의 차동 디지털-아날로그 변환기 (DAC: digital-to-analog converter)를 이용하는 10-bit 10-MS/s 비동기 축차근사형 (SAR: successive approximation register) 아날로그-디지털 변환기 (ADC: analog-to-digital converter)를 제안한다. 샘플링 주파수를 증가시키기 위해 SAR 로직과 비교기는 비동기로 동작을 한다. 또한 높은 해상도를 구현하기 위해 오프셋 보정기법이 적용된 시간-도메인 비교기를 사용한다. 제안하는 10-bit 10-MS/s 비동기 축차근사형 아날로그-디지털 변환기는 0.18-${\mu}m$ CMOS 공정에서 제작되며 면적은 $140{\times}420{\mu}m^2$이다. 1.8 V의 공급전압에서 전력소모는 1.19 mW이다. 101 kHz 아날로그 입력신호에 대해 측정된 SNDR은 49.95 dB이며, DNL과 INL은 각각 +0.57/-0.67, +1.73/-1.58이다.

Keywords

References

  1. Cho, S.-H., Lee, C.-K., Kwon, J.-K. and Ryu, S.-T. "A 550-uW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction." IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1881-1892, Aug. 2011. https://doi.org/10.1109/JSSC.2011.2151450
  2. S.-K. Lee, S.-J. Park, Y. Suh, H.-J. Park, and J.-Y. Sim, "A 1.3$\mu$W 0.6V 8.7-ENOB Successive Approximation ADC in a 0.18$\mu$m CMOS," in Proc. IEEE VLSI Circuit Symp, pp.242-243, Jun.,2009.
  3. C.C. Liu, et. al., "A 10-bit 50-MS/s SAR ADC with a Monotonic Capacitor Switching Procedure," IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010. https://doi.org/10.1109/JSSC.2010.2042254
  4. J. Yang, T. L. Naing, and R. W. Brodersen, "A 1 GS/s 6 Bit 6.7 mW successive approximation ADC using asynchronous processing," IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1469-1478, Aug. 2010. https://doi.org/10.1109/JSSC.2010.2048139
  5. S.-W.M. Chen and R. W. Brodersen, "A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13-$\mu$m CMOS," IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669-2680, Dec. 2006. https://doi.org/10.1109/JSSC.2006.884231
  6. T. Jiang, W. Liu, F. Y. Zhong, C. Zhong, K. Hu and P. Y. Chiang, "A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Syccessive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS," IEEE J. Solid-State Circuits, vol. 47, no. 10, pp. 2444-2453, Oct. 2012. https://doi.org/10.1109/JSSC.2012.2204543