한국통신학회논문지 (The Journal of Korean Institute of Communications and Information Sciences)

한국통신학회 (The Korean Institute of Commucations and Information Sciences)
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효율적인 ASIP 설계를 위한 자동 인스트럭션 확장 시스템 구축

Construction of an Automatic Instruction-Set Extension System for Efficient ASIP Design

  • 황덕호 (서강대학교 전자공학과 CAD & ES 연구실) ;
  • 황선영 (서강대학교 전자공학과 CAD & ES 연구실)
  • 투고 : 2012.11.26
  • 심사 : 2012.12.11
  • 발행 : 2013.01.31
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초록

본 논문은 어플리케이션에 최적화된 ASIP설계를 하기 위해 MDL을 기반으로 한 Retargetable 컴파일러를 이용한 자동 인스트럭션 확장 시스템을 제안한다. 제안된 시스템은 어플리케이션 프로그램으로부터 얻은 정보를 이용하여 확장 가능한 인스트럭션 후보를 모두 찾는다. 확장 인스트럭션 후보는 하드웨어 라이브러리를 통해 실제 구현 시의 특성에 대한 정보를 얻게 된다. 하드웨어 특성과 수행 속도 향상을 기반으로 주어진 제한 조건에 맞게 인스트럭션 셋을 선택하고 프로세서 구조를 최적화한다. 제안된 시스템의 효용성을 확인하기 위해 다양한 벤치마크 어플리케이션을 이용하여 자동 인스트럭션 확장 시스템을 수행하였다. 제안된 시스템은 기존의 ARM9TDMI의 프로세서로부터 최적화된 인스트럭션 셋과 프로세서 구조를 갖도록 하였다. 제안된 시스템에 의해 설계된 ASIP는 주어진 제한 조건에 따라 기존 프로세서와 비교하면 평균 33.5%의 수행 사이클이 감소하는 것으로 확인되지만, 프로세서의 면적은 증가하는 것으로 측정되었다.

This thesis proposes an automatic instruction extension system that utilizes retargetable compiler, based on MDL, to design an ASIP optimized for application. The proposed system uses information gathered from the application program to find all possible expandable instruction candidates. Expandable instruction candidates acquire the realization characteristics through hardware library. The system chooses instruction set and optimizes processor structure satisfying constraints on the bases of hardware characteristics and increase in execution speed. To confirm the efficiency of the proposed system, automatic instruction extension system was performed using various benchmark applications. The proposed system acquired optimized instruction set and processor structure, which are expanded from the commercial version of ARM9TDMI. Experimental results show that number of execution cycle has been reduced by 33.5% when compared to conventional version of ARM9TDMI, while area has been slightly increased.

키워드

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