전기전자학회논문지 (Journal of IKEEE)

  • 제17권4호
  • /
  • Pages.511-516
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  • 2013
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  • 1226-7244(pISSN)
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  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
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새로운 FDPA 기법을 사용한 시그마-델타 변조기

Sigma-Delta Modulator using a novel FDPA(Feedback Delay Path Addition) Technique

  • Jung, Eui-Hoon (Dept. of Electronics Engineering, Chonbuk University) ;
  • Kim, Jae-Bung (Dept. of Electronics Engineering, Chonbuk University) ;
  • Cho, Seong-Ik (Dept. of Electronics Engineering, Chonbuk University)
  • 투고 : 2013.11.04
  • 심사 : 2013.12.02
  • 발행 : 2013.12.30
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 DAC(Digital to Analog Converter) 출력을 지연시켜 디지털 피드백 패스를 추가하는 FDPA 기법을 사용한 SDM(Sigma Delta Modulator)을 제안한다. 지연된 디지털 피드백 패스만을 추가하여 SDM의 해상도를 높이고 기존 구조의 아날로그 피드백 패스를 제거함으로써 기존 구조에 비해 사용되는 클록이 줄어들어 회로가 간단하다. 제안한 구조를 설계하기 위해 MATLAB 모델링을 이용하여 적분기의 최적 계수를 설정하였다. 설계된 SDM은 $0.18{\mu}m$ CMOS 공정을 사용하였고 신호 대역폭 20KHz, 샘플링 주파수 2.56MHz에서 81dB의 SNR, $220{\mu}W$의 전력을 소모한다.

This paper presents a SDM using the FDPA technique. The FDPA technique is the added feedback path which is the delayed path of DAC output. The designed SDM increases the SNR by adding the delayed digital feedback path. The proposed SDM is easily implemented by eliminating the analog feedback path. Through the MATLAB modeling, the optimized coefficients are obtained to design the SDM. The designed SDM has a power consumption of $220{\mu}W$ and SNR(signal to noise ratio) of 81dB at the signal-bandwidth of 20KHz and sampling frequency of 2.56MHz. The SDM is designed using the $0.18{\mu}m$ standard CMOS process.

키워드

참고문헌

  1. James C.Morizio, Michael Hoke, Taskin Kocak, Clark Geddie, Chris Hughes, John Perry, Srinadh Madhavapeddi, Michael H. Hood, George Lynch, Harufusa Kondoh, Toshio Kumamoto, Takashi Okuda, Hiroshi Noda, Masahiko Ishiwaki, Takahiro Miki, and Masao Nakaya "14-bit 2.2-MS/s Sigma-Delta ADC's," IEEE J. Solid-State Circuits, vol. 35, No. 7, pp. 968-976, July. 2000 https://doi.org/10.1109/4.848205
  2. Daisuke Kanemoto, Toru Ido and Kenji Taniguchi, "A 7.5mW 101dB SNR Low-Power High-Performance Audio Delta-Sigma Modulator Utilizing Opamp Sharing Technique" SoC Design Conference(ISOCC), 2011 International, pp. 66-69. 2011.
  3. Chuan-Hung Hsiao, Wei-Lin Chen, Chih-Cheng Hsieh , "A 0.8V 80.3dB SNDR Stage-Shared ${\Delta}{\Sigma}$ Moudulator with chopper-Embeded Switched-Opamp for Biomedical Application", IEEE Asian Solid-State Circuits Conference, IPEC.2012.6522673, pp. 253-256, 2012.
  4. Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi, Takayasu Sakurai, "Managing Subthreshold Leakage in Charge-BasedAnalog Circuits With Low-Vth Transistors by Analog TSwitch (AT-Switch) and Super Cut-off CMOS (SCCMOS), IEEE J. Solid-State Circuits, vol. 41, No. 4, pp. 859-867, Apr. 2006 https://doi.org/10.1109/JSSC.2006.870761
  5. J. Koh, Y. Chio, and G. Gomez, "A 66dB DR 1.2V 1.2mW single-amplifier double-sampling 2nd-order ${\Delta}{\Sigma}$ ADC for WCDMA in 90nm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2005, vol. 1, pp. 170-171.
  6. Chuc K. Thanh, Stephen H. Lewis, and Paul J. Hurst, "A Second-Order Double-Sampled Delta-Sigma Modulator Using Individual-Level Averaging" IEEE J . Solid-State Circuits, vol. 32, No. 8, pp. 1269-1273, Aug. 1997. https://doi.org/10.1109/4.604085
  7. Gun-Hee Yun. "Design of A Low-Power 12-Bit Sigma-Delta Modulator" Hanyang University. 2011.
  8. David A. Johns, Ken Martin, "Analog Integrated circuit design", pp. 542-571. 1997

피인용 문헌

  1. 3rdSDM with FDPA Technique to Improve the Input Range vol.18, pp.2, 2014, https://doi.org/10.7471/ikeee.2014.18.2.192