참고문헌
- J. B. Kuo and S C. Lin, "Low voltage SOI CMOS VLSI devices and circuits," John Wiley & Sons. INC. 2001.
- S. Monfray et.al, "First 80nm SON (Silicon On Nothing) MOSFETs with perfect morphology and high electrical performance," Electron Devices Meeting, 2001. IEDM 2007. Digest of Technical Papers. IEEE International, pp. 29.7.1 - 29.7.4, 2001.
- M. Jurczak et.al. "Dielectric Pockets—A New Concept of the Junctions for Deca-Nanometric CMOS Devices," Electrons Devices, IEEE Transactions on. Vol. 48, pp. 1770-1774, 2001. https://doi.org/10.1109/16.936706
- V. Kumari, M. Saxena, R. S. Gupta, and M. Gupta, "Simulation Study of Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for High Temperature Applications," Microelectronics Reliability, Vol. 52, no. 8, pp. 1610-1612, 2012. https://doi.org/10.1016/j.microrel.2011.10.022
- V. Kumari, M. Saxena, R. S. Gupta, and M. Gupta, "Temperature dependent drain current model for Gate stack Insulated Shallow extension silicon On Nothing MOSFET for wide range of operating temperatures," Microelectronics Reliability, Vol. 52, no. 6, pp. 974-983, 2012. https://doi.org/10.1016/j.microrel.2011.12.021
- R. Kaur, R. Chaujar, M. Saxena, and R. S. Gupta, "Hot-Carrier Reliability and Analog Performance Investigation of DMG-ISEGaS MOSFET," Electrons Devices, IEEE Transactions on. Vol. 54, no. 9, pp. 2556-2561, 2007. https://doi.org/10.1109/TED.2007.902855
- V. Kumari, M. Saxena, R. S. Gupta, and M. Gupta, "Laterally Asymmetric Channel Insulated Shallow Extension Silicon On Nothing LAC-ISE-SON MOSFET for Improved Reliability and digital circuit Simulation," International conference on Devices, circuit and system (ICDCS-2012), pp. 282-292, 15-16 March, 2012.
- N H E. Weste, D. Harris and A. Banerjee, "CMOS VLSI design: A circuit and system perspective," Dorling Kindersley (India) Pvt. Ltd. 2006.
- ATLAS: 3-D Device Simulator, SILVACO International, Version 5.14.0.R, 2010.
- M. Jurczak et.al., „ Silicon On Nothing- an Innovative Process for Advanced CMOS," Electrons Devices, IEEE Transactions on. Vol. 47, pp. 2179- 2187, 2000. https://doi.org/10.1109/16.877181
- V. Kumari, M. Saxena, R. S. Gupta, and M. Gupta "Simulation Study of Gate Stacked Insulated Shallow Extension Silicon On Nothing ISE-SON MOSFET for RFICs design," Student's Technology Symposium, 2011, IEEE International, 14th -16th, Vol. 42, Jan. 2011; 42.
- A. Kranti, and G. A. Armstrong, "Nonclassical channel design in MOSFETs for improving OTA gain bandwidth trade-off," Circuits and Systems II, IEEE Transactions on.Vol. 57, no.12, pp. 3048- 3054, 2010. https://doi.org/10.1109/TCSI.2010.2071470
- J L. Rossello, and J. Segura, "An analytical charge based compact delay model for submicrometer CMOS inverters," Circuits and Systems I, IEEE Transactions on. Vol. 51, no. 7, pp. 1301-1311, 2004. https://doi.org/10.1109/TCSI.2004.830692
- S. Kaya, H. F. A. Hamed, J. A. Starzyk, "Low power tunable analog circuit blocks based on Nanoscale double gate MOSFETs," Circuits and Systems II, IEEE Transactions on. Vol. 54, No. 7, pp. 571-575, 2007. https://doi.org/10.1109/TCSII.2007.895324
- S. Ghosh, K. J. Singh, S. Deb, and S. K. Sarkar, "Two Dimensional Analytical Modeling for SOI and SON MOSFET and their Performance Comparison," Journal of Nano- and Electronics Physics, Vol. 3, no. 1, pp. 569-575, 2011.
- C. H. Shih, Y. M. Chen, and C. Lien, "An insulated shallow extension structure for bulk MOSFET,". Electrons Devices, IEEE Transactions on. Vol. 50, no. 11, pp. 2294-2297, 2003. https://doi.org/10.1109/TED.2003.818284
- J. R. Hauser, "Noise margin criteria for digital logic circuits," Education, IEEE Transactions on. Vol 36, no. 4, pp. 363-368, 1993. https://doi.org/10.1109/13.241612
- K. D. Buddharaju et. al., "Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach," Solid State Electronics, Vol. 52, no.9, pp. 1312-1317, 2008. https://doi.org/10.1016/j.sse.2008.04.017
- I. Y. Chung, Y. J. Park, and H. S. Min, "A New SOI Inverter Using Dynamic Threshold for Low- Power Applications," Electron. Device Letters, IEEE, Vol. 18, no. 6, pp. 248-250, 1997. https://doi.org/10.1109/55.585343