References
- Novak, O. and Charles, C. and Brown, R.B., "A fully integrated 19 pJ/pulse UWB transmitter for biomedical applications implemented in 65 nm CMOS technology", IEEE International Conference on Ultra-Wideband (ICUWB), pp.72-75, Sept. 2011.
- Hart, J. et al., "3.6GHz 16-core SPARC SoC processor in 28nm", IEEE International Solid-State Circuits Conference, pp. 48-49, Feb. 2013.
- Zianbetov, E. et al."A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation", IEEE International Symposium Circuits and Systems (ISCAS), pp. 2845-2848, May. 2011.
- Y. G. Song, Y. S. Choi J. G. Ryu, "A Fast Locking Phase Locked Loop with Multiple Charge Pumps", Journal of the Institute of Electronics Engineers of Korea-SD vol. 46 no. 2, pp. 71-77, Feb. 2009.
- Y. T. Kim et al., "A low-power programmable DLL-based clock generator with wide-range anti-harmonic lock", International SoC Design Conference (ISOCC), pp. 520-523, Nov. 2009.
- K. H. Ryu and D. H. Jung and S. O. Jung, "A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator", IEEE Transactions On Circuits And Systems-I: Regular Papers, vol. 53, no. 5, pp. 1860-1870, May. 2006. https://doi.org/10.1109/TCSI.2006.882332
- S. W. Hwang et al., "A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor", IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 21, no. 3, pp. 575-579, March. 2013. https://doi.org/10.1109/TVLSI.2012.2188656
- Po-Chun Huang et al, "A phase error calibration DLL with edge combiner for wide-range operation", New Circuits and Systems Conference (NEWCAS), 2011 IEEE 9th International, pp.1-4, June. 2011.
- J. H. Nam, Y. S. Choi, "A Clock Generator with Jitter Suppressed Delay Locked Loop" Journal of the Institute of Electronics Engineers of Korea-SD, vol. 49 no. 7, pp.17-22, July. 2012. https://doi.org/10.5573/ieek.2012.49.11.017
- K. J. Hsiao and T. C. Lee, "An 8-GHz to 10-GHz distributed DLL for multiphase clock generation," IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2478-2487, Sept. 2009. https://doi.org/10.1109/JSSC.2009.2024804
- John G. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996. https://doi.org/10.1109/JSSC.1996.542317
- G. Chien and P. R. Gray, "A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications", IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1996 -1999, Dec. 2000. https://doi.org/10.1109/4.890315