DOI QR코드

DOI QR Code

비전도성 접착제로 국부적으로 둘러싸인 인터록킹 접속구조를 이용한 플립칩 공정

A Flip Chip Process Using an Interlocking-Joint Structure Locally Surrounded by Non-conductive Adhesive

  • 투고 : 2012.05.02
  • 발행 : 2012.10.25

초록

A new flip chip structure consisting of interlocking joints locally surrounded by non-conductive adhesive was investigated in order to improve the contact resistance characteristics and prevent the parasitic capacitance increase. The average contact resistance of the interlocking joints was substantially reduced from $135m{\Omega}$ to $79m{\Omega}$ by increasing the flip chip bonding pressure from 85 MPa to 185 MPa. Improvement of the contact resistance characteristics at higher bonding pressure was attributed not only to the increased contact area between Cu chip bumps and Sn pads, but also to the severe plastic deformation of Sn pads caused during formation of the interlocking-joint structure. The parasitic capacitance increase due to the non-conductive adhesive locally surrounding the flip chip joints was estimated to be as small as 12.5%.

키워드

과제정보

연구 과제 주관 기관 : 교육과학기술부

참고문헌

  1. M. H. Roh, H. Y. Lee, W. Kim, and J. P. Jung, J. Korean J. Met. Mater. 49, 411 (2011).
  2. J. W. Wan, W. J. Zhang, and D. J. Bergstrom, J. Microelectron. Reliab. 38, 67 (2007).
  3. L. Han and J. Zhong, J. Microelectron. Eng. 85, 1568 (2008).
  4. Y. N. Kim, J. M. Koo, S. K. Park, and S. B. Jung, J. Kor. Inst. Met. & Mater. 46, 33 (2008).
  5. M. Y. Kim, S. K. Lim, and T. S. Oh, J. Microelectron. Packag. Soc. 17, 27 (2010).
  6. K. N. Tu and K. Zeng, Mater. Sci. Eng. 34, 1 (2001).
  7. S. K. Lim, J. W. Choi, Y. H. Kim, and T. S. Oh, J. Kor. Inst. Met. & Mater. 46, 585 (2008).
  8. T. S. Oh, K. Y. Lee, Y. H. Lee and B. Y. Jung, Met. Mater. Int. 15, 479 (2009).
  9. U. B. Kang, and Y. H. Kim, IEEE Trans. Comp. Packag. Technol. 27, 253 (2004).
  10. J. Y. Choi, M. Y. Kim, S. K. Lim, and T. S. Oh, J. Microelectron. Packag. Soc. 16, 67 (2009).
  11. J. Laskar, A. Sutono, C. H. Lee, M. F. Davis, A. Obatoyinbo, K. Lim, and M. Tentzeris, Proc. IEEE GaAs IC Symp., p.215, IEEE, Baltimore, USA (2001).
  12. J. H. Lau, Flip Chip Technologies, p.25-59, McGraw- Hill, New York (1995).
  13. J. Audet, L. Belanger, G. Brouilette, D. Danovitch, and V. Oberson, Proc. Int. Flip Chip, Ball Grid Array, TAB & Adv. Packag. Symp. (ITAP 95), p.16, San Jose, USA (1995).
  14. M. J. Yim, J. S. Hwang, W. S. Kwon, K. W. Jang, and K. W. Paik., Proc. 52nd Electron. Comp. Technol. Conf, p.1385, IEEE, San Diego, USA (2002).
  15. T. S. Oh, K. Y. Lee, and H. J. Won, IEEE Trans. Comp. Packag. Technol. 32, 909 (2009).
  16. M. Datta, T. Osaja, and J. W. Schultze, Microelectronic Packaging, p.191, CRC Press, New York (2005).
  17. A. O. Aggarwal, P. M. Raj, I. R. Abothu, M. D. Sacks, A. A. Tayl, and R. R. Tummala, Proc. 54th Electron. Comp. Technol. Conf, p.451, IEEE, Las Vegas, USA (2004).
  18. Metals Handbook, Properties and Selection of Metals 8th ed., p.1142, American Society for Metals, Metals Park (1969).
  19. D. K. Schroder, Semiconductor Material and Device Characterization 2nd ed., pp.345-357, John Wiley & Sons, New York (1998).
  20. C. Y. Yin, M. O. Alam, Y. C. Chan, C. Bailey, and H. Lu, Microelectron. Reliab., 43, 625 (2003).
  21. H. Kristiansen and J. Liu, IEEE Trans. CPMT-A 21, 208 (1998).
  22. K. Ishibashi and J. Kimura, IEEE Trans. CPMT-B 19, 752 (1996).
  23. D. C. Giancoli, Physics, Principles with Applications 5th ed., pp.568-570, Prentice Hall, Upper Saddle River, New Jersey (1998).
  24. Z. G. Chen and Y. H. Kim, Displays 27, 130 (2006).
  25. H. D. Dong, Y. Li, M. J. Yim, K. S. Moon, and C. P. Wong, Appl. Phys. Lett. 90, 092102 (2007).