Journal of Power Electronics

  • 제12권6호
  • /
  • Pages.947-953
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  • 2012
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  • 1598-2092(pISSN)
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  • 2093-4718(eISSN)
전력전자학회 (The Korean Institute of Power Electronics)
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Electrical Characteristics and Thermal Reliability of Stacked-SCRs ESD Protection Device for High Voltage Applications

  • Koo, Yong Seo (Dept. of Electronics and Electrical Eng., Dankook University) ;
  • Kim, Dong Su (Dept. of Electronics and Electrical Eng., Dankook University) ;
  • Eo, Jin Woo (Dept. of Electronics and Electrical Eng., Dankook University)
  • 투고 : 2012.04.13
  • 발행 : 2012.11.20
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초록

The latch-up immunity of the high voltage power clamps used in high voltage ESD protection devices is very becoming important in high-voltage applications. In this paper, a stacking structure with a high holding voltage and a high failure current is proposed and successfully verified in 0.18um CMOS and 0.35um BCD technology to achieve the desired holding voltage and the acceptable failure current. The experimental results show that the holding voltage of the stacking structure can be larger than the operation voltage of high-voltage applications. Changes in the characteristics of the stacking structure under high temperature conditions (300K-500K) are also investigated.

키워드

참고문헌

  1. J. B. Huang and G. Wang, "ESD protection design for advanced CMOS," Proc. SPIE, pp. 123-131, 2001.
  2. Young Chung, "Snapback Breakdown Dynamics and ESD Susceptibility of LDMOS," Reliability Physics Symposium, pp. 352-355, Mar. 2006.
  3. V. Vashchenko, A. Concannon, M. ter Beek, and P. Hopper, "High holding voltage cascoded LVTSCR structures for 5.5-V tolerant ESD protection clamps," IEEE Transactions on Devices and Materials Reliability, Vol. 4, pp. 273-280, 2004. https://doi.org/10.1109/TDMR.2004.826584
  4. M. D Ker and H.-H. H.-H. Chang, "How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on," Journal of Electro- statics, Vol. 47, pp. 215-248, Oct. 1999. https://doi.org/10.1016/S0304-3886(99)00037-6
  5. Y. Koo, K. Lee, K. Kim, and J. Kwon, "Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology," Microelectronics Journal, Vol. 40, pp. 1007-1012, Jun. 2009. https://doi.org/10.1016/j.mejo.2009.01.001
  6. S.-L. Jang, L.-S. Lin, and S.-H Li, "Temperature-dependent dynamic triggering characteristics of SCR-type ESD protection circuits," Solid-State Electronics, Vol. 45, pp. 2005-2009, 2001. https://doi.org/10.1016/S0038-1101(01)00243-X
  7. W. Y. Chen, M.-D. Ker, Y.-J. Huang, Y.-N. Jou, and G.-L. Lin, "Measurement on Snapback Holding voltage of High-Voltage LDMOS for Latch-up Consideration," circuit and system, APCCAS 2008, pp. 61-64, 2008.

피인용 문헌

  1. A Novel High Latch-Up Immunity Electrostatic Discharge Protection Device for Power Rail in High-Voltage ICs vol.16, pp.2, 2016, https://doi.org/10.1109/TDMR.2016.2544350