The Proceeding of the Korean Institute of Electromagnetic Engineering and Science (한국전자파학회지:전자파기술)

The Korean Institute of Electromagnetic Engineering and Science (한국전자파학회)
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PCB 및 IC회로에서의 EMC 기술 연구 동향

  • 육종관 (연세대학교 전기전자공학과) ;
  • 나완수 (성균관대학교 정보통신공학부)
  • Published : 2012.07.31
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Abstract

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References

  1. http://www.itrs.net/reports.html
  2. Bruce Archambeault Colin Brench, and Sam Connor, "Review of printed-circuit-board level EMI/EMC issues and tools", IEEE Transactions on Electromagnetic Compatibility, vol. 52, no. 2, pp. 455-461, May 2010. https://doi.org/10.1109/TEMC.2010.2044182
  3. Mohamed Ramdani, Etienne Sicard, Alexandre Boyer, Sonia Ben Dhia, James J. Whalen, Todd H. Hubing, Mart Coenen, and Osami Wada, "The electromagnetic compatibility of integrated circuits-past, present, and future", IEEE Transactions on Electromagnetic Compatibility, vol. 51, no.1, pp.78-100, Feb. 2009. https://doi.org/10.1109/TEMC.2008.2008907
  4. Dong G. Kam, Mark B. Ritter, Troy J. Beukema, John F. Bulzacchelli, Petar K. Pepeljgoski, Young H. Kwark, Lei Shan, Xiaoxiong Gu, Christian W. Baks, Richard A. John, Gareth Hougham, Christian Schuster, Renato Rimolo-Donadio, and Boping Wu "Is 25 Gb/s on-board signaling viable?", IEEE Transactions on Advanced Packaging, vol. 32, no. 2, pp. 328-344, May 2009. https://doi.org/10.1109/TADVP.2008.2011138
  5. Mohamed Ramdani , Etienne Sicard, Sonia Ben Dhia, and Johan Catrysse, "Towards an EMC roadmap for integrated circuits", Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, pp. 8-11, 19-23 May 2008.
  6. Stephen H. Hall, Howard L. Heck, Advanced Signal Integrity for High-speed Digital Designs, John Wiley & Sons, Inc., 2009.
  7. W. Pan, S. Connor, and B. Archambeault, "Prediction noise voltage from trace crossing split planes on printed circuit boards", IEEE Inter. Symp. on Electromagnetic Compatibility, pp. 45-50, Aug. 2009.
  8. X. Duan, B. Archambeault, Heinz-D. Bruns, and C. Schuster, "EM emission of differential signals across connected printed circuit boards in the GHz rage" IEEE Inter. Symp. on Electromagnetic Compatibility, pp. 50-55, Aug. 2009.
  9. R. Senthinathan, J. L. Prince, "Simultaneous switching ground noise calculation for packaged CMOS devices", Solid-State Circuits, IEEE Journal, vol. 26, no. 11, pp. 1724-1728, 1991.
  10. A. Vaidyanath, B. Thorddsen, and J. L. Prince, "Effect of CMOS driver loading conditions on simultaneous switching noise", Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on, vol.17, no.4, pp.480-485, 1994.
  11. L. D. Smith, R. E. Anderson, D. W. Forehand et al., "Power distribution system design methodology and capacitor selection for modem CMOS technology", Advanced Packaging, IEEE Transactions on, vol.22, no.3, pp.284-291, 1999.
  12. M. Swaminathan, J. Kim, J. Novak, and J. P. Libous, "Power distribution networks for system-onpackage: Status and challenges", IEEE Trans. Adv. Packag., vol. 27, no. 2, pp. 286-300, May 2004. https://doi.org/10.1109/TADVP.2004.831897
  13. J. Lee, M. D. Rotaru, M. K. Iyer, H. Kim, and J. Kim, "Analysis and suppression of SSN noise coupling between power/ground plane cavities through cutouts in multi layer packages and PCBs", IEEE Trans. Adv. Packag., vol. 28, no. 2, pp. 298-309, May 2005. https://doi.org/10.1109/TADVP.2005.846932
  14. T.-L. Wu, J. Fan, F. d. Paulis, C.-D. Wang, A. C. Scogna, and A. Orlandi, "Mitigation of noise coupling in multilayer high-speed PCB: state of the art modeling methodology and EBG technology", IEICE Trans. Commun. (Invited paper), vol. E93-B, no. 07, Jul. 2010.
  15. T.-L. Wu, C.-C. Wang, Y.-H. Lin, T.-K Wang, and G. Chang, "A novelpower plane with super wideband elimination of ground bounce noise on high speed circuits", IEEE Microw. Wireless Compon. Lett., vol. 15, no. 3, pp. 174-176, Mar. 2005. https://doi.org/10.1109/LMWC.2005.844216
  16. F. de Paulis, A. Orlandi, L. Raimondo, B. Archambeault, and S. Connor, "Common mode filtering performances of planar EBG structures", IEEE Int. Symp on Electromagnetic Compatibility, pp. 86-90, Aug. 2009.
  17. J. L. Knigbten, B. Archambeault, J. Fan, G. Selli, S. Connor, and J. L. Drewniak, "PDNDesign strategies: I. ceramic SMT decoupling capacitors - what values should Ichoose?", IEEE EMC Society Newsletter, issue no. 207, pp. 46-53, Fall 2005.
  18. Hyungsoo Kim, et al., "High dielectric constant thin film embedded capacitor for suppression of simultaneous switching noise and radiated emission", in Proc. IEEE Inter Symp. on Electromagnetic Compatibility, vol. 2, pp. 588-591, Aug. 2004.
  19. B. D. McCredie, W. D. Becker, "Modeling, measurement, and simulation of simultaneous switching noise", IEEE Trans. Comp. Packag. Manufact. Technol. B, vol. 19, pp. 461-472, Aug. 1996. https://doi.org/10.1109/96.533884
  20. M. P. Robinson, et al., "Effect of logic family on radiated emissions from digital circuits", IEEE Trans. Electromagn. Compat., vol. 40, pp. 288-293, Aug. 1998. https://doi.org/10.1109/15.709429
  21. F. Fiori, "Analysis of EME produced by a microcontroller operation" , Conference and Exhibition on Design, Automation and Test in Europe, pp. 341-345, 2001.
  22. Howard H. Chen, J. Scott Neely, "Interconnect and circuit modeling techniques for full-chip power supply noise analysis", IEEE Transactions on Components, Packaging, and Manufacturing Technology - Part B: Advanced Packaging, vol. 21, no. 3, pp. 209- 215, Aug. 1998.
  23. S. Zhao, K Roy, and C. Koh, "Decoupling capacitance allocation 뻐d its application to power supply noise aware floor planning", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol . 21, no. 1, Jan. 2002.
  24. Sachio Hayashi, Masaaki Yamada, "EMI-noise analysis under ASIC design environment" , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 11, Nov. 2000.
  25. K. B. Hardin, J. T. Fessler, and D. R. Bush, "Spreadspectrum clock generation for the reduction of radiated emissions", Proc. IEEE Int. Symp. Electromagnetic Compatibility, pp. 227-231, 1994.
  26. T. Steinecke, "Design-In for EMC on CMOS lagescale integrated circuits", IEEE International Symposium on Electromagnetic Compatibility, vol. 2, pp. 910-915, 2001.
  27. J. M. Hobbs, H. Windlass, V. Sundaram, S. Chun, G. E. White, M. Swaminathan, and R. R. Tummala, "Simultaneous switching noise suppression for high speed systems using embedded decoupling", Proceeding Electron. Comon Technol. Conference 2001, pp. 339-343, 2001.
  28. J.- J. Laurin, S. G. zaky, and K. G. Balmain "Prediction of delays induced by in-band RFI in CMOS inverters", IEEE Trans. Electromagn. Compat., vol. 37, pp. 167-174, May 1995. https://doi.org/10.1109/15.385879
  29. I. D. Flintoft, A. C. Marvin, M. P. Robinson, K. Fischer, and A. J. Rowell, "The re-emission spectrum of digital hardware subjected to EMI", IEEE Transactions on EMC, vol. 45, no. 4, pp. 576-85, 0018-9375, Nov. 2003.
  30. K. Murano, H. Kawahara, M. Tayarani, Fengchao Xiao, and Y. Kami, "New radiated immunity/susceptibility test method using four-septum TEM cell: Measurements and field analysis" Proc. IEEE lnt. Symp. Electromagnetic Compatibility, pp. 1-6, Jul. 2007.
  31. M. P. Robinson, et al., "Susceptibility of personal computer systems to fast transient electromagnetic pulses", IEEE Trans. Electromagn. Compat., vol. 48, no. 4, Nov. 2006.
  32. R. E. Walllace, S. G. Zaky, and K. G. Balmain, "Fast-transient susceptibility of a D-type flip-flop", IEEE Trans. Electromagnetic Compatibility, vol. 37, no. 1, pp. 75-80, Feb. 1995. https://doi.org/10.1109/15.350243
  33. S. T. Bakshi, M. Coenen, "Impulse immunity test method for digital integrated circuits", International Conference on Electromagnetic Interference and Compatibility, pp. 249-252, Dec. 2003.
  34. John F. Chappel, Safwat G. Zaky" "EMI effects and timing design for increased reliability in digital systems", IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, vol. 44, no. 2, Feb. 1997.
  35. G. F. Bouesse, N. Ninon, G. Sicard, M. Renaudin, A. Boyer, and E. Sicard, "Asynchronous logic vs synchronous logic: Concrete results on electromagnetice missions and conducted susceptibility", Presented at the EMCCompo 2007, Torino, Italy, Nov. 2007.
  36. A. Alaeldine, N. Lacrampe, J. L. Levant, R. Perdriau, M. Ramdani, and F. Caignet, "Efficiency of embedded on-chip EMI protections to continuousharmonic and fast tranlsient pulses with respect to substrate injection", Proc. IEEE Symp. EMC 2007, pp. 1-5, Jul. 2007.